EPC1LC20-WCEC52 - 1Mb OTP Config PROM, 20-PLCC | Altera
MPN: EPC1LC20-WCEC52 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.45 | $7,450.00 |
EPC1LC20-WCEC52 Overview
What is a configuration PROM? In FPGA-based systems, SRAM-based LUT devices are volatile and must be reloaded from non-volatile memory every time they power up. A configuration PROM is a dedicated serial flash-like memory that holds the FPGA bitstream and streams it to the FPGA during the configuration phase via a standardized serial protocol (typically FPP or PS mode on Altera devices). Within the broader component hierarchy, the EPC1 sits below memory IC and above general-purpose serial flash: configuration PROM -> serial configuration memory -> non-volatile memory -> memory IC -> semiconductor.
Key features include an 8 MHz configuration clock, low-power CMOS process, hardware reset pin, JTAG-compliant ISP, and dedicated open-drain CONF_DONE and nSTATUS handshake lines. The part supports 3.3 V and 5.0 V operation and replaces the older EPC1 family while maintaining pin compatibility with the 20-pin PLCC footprint used across the original EPC1 generation.
Architecturally, the EPC1LC20 uses an internal oscillator, a serial state machine, and an internal charge pump to drive the OTP cells during programming. It exposes only four active signals to the FPGA: nCS, DATA, DCLK, and nCONFIG, keeping board routing simple. Read access during configuration is sequential; once nCONFIG is asserted and nSTATUS goes high, the device clocks out the bitstream on the rising edge of DCLK until CONF_DONE is asserted.
Typical applications include standalone FPGA configuration storage for Cyclone II/III prototyping boards, factory programming for production Altera FPGA modules, JTAG-programmable single-FPGA designs, and design migration paths where older EPC1/EPC2 PROMs are being requalified. The 20-PLCC through-hole footprint also suits legacy industrial control and test equipment where socketed configuration memory is preferred for in-field bitstream updates.
When designing with this part, note that the OTP array cannot be re-erased - the JTAG ISP path performs the one and only programming operation. Ensure your JTAG chain order and TMS/TCK termination match the IEEE 1149.1 specification, and decouple VCC with a 0.1 uF ceramic capacitor placed within 5 mm of the supply pin to suppress programming-induced transients.
This page synthesizes distributor pricing, drop-in alternatives in the same 20-PLCC footprint, and practical configuration-routing design notes that go beyond what is printed in the original Altera datasheet.
Drop-in alternatives for EPC1LC20-WCEC52 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1LC20-WCEC52 (same form factor and footprint) — differing in Memory Type, Package, Mounting Type, Interface, Compatible FPGA Families.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20-W
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPC1LC120
✅ Drop-In✓ In Stock
$9.3 / Unit
View Datasheet →EPC1L20
✅ Drop-In✓ In Stock
$3.75 / Unit
View Datasheet →EPC1441LC20
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC1L120
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC1LC20-WCEC52 Maximum Ratings & Electrical Characteristics
| Memory Type | OTP Configuration PROM (Anti-fuse) |
| Memory Size | 1 Mbit (1,048,576 bits) |
| Organization | 212,942 x 1 bit |
| Interface | Serial (Altera FPP/PS configuration protocol) |
| Configuration Clock (DCLK) | 8 MHz maximum |
| Supply Voltage (VCC) | 3.3 V |
| I/O Voltage Tolerance | 5.0 V (FPGA interface) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Programmability | One-Time Programmable (OTP) |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 20-pin PLCC (J-lead, through-hole, 9x9 mm) |
| Package Mounting | Through-hole (also accepts PLCC socket) |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, MAX series |
| Programming Interface | JTAG (IEEE Std 1149.1) ISP |
| Pin Count | 20 |
| Lifecycle Status | Obsolete (recommended replacement: EPCQ family or newer serial config devices) |
EPC1LC20-WCEC52 Pin Configuration
| Pin 1 | VCC — 3.3 V supply voltage |
| Pin 2 | nCS — Chip select (active low) |
| Pin 3 | DATA — Serial configuration data output |
| Pin 4 | DCLK — Configuration clock input |
| Pin 5 | nCONFIG — Configuration request (active low) |
| Pin 6 | nSTATUS — Configuration status (open-drain, active low) |
| Pin 7 | CONF_DONE — Configuration complete (open-drain) |
| Pin 8 | GND — Ground |
| Pin 9 | TDI — JTAG test data in |
| Pin 10 | TMS — JTAG test mode select |
| Pin 11 | TCK — JTAG test clock |
| Pin 12 | TDO — JTAG test data out |
| Pin 13 | NC — Not connected |
| Pin 14 | NC — Not connected |
| Pin 15 | NC — Not connected |
| Pin 16 | NC — Not connected |
| Pin 17 | NC — Not connected |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | NC — Not connected |
Typical Applications
EPC1LC20-WCEC52 is suitable for 7 applications: Standalone FPGA Configuration Storage, Legacy Industrial Control Board, JTAG-Programmable Development Board, Avionics and Defense Retrofit, Test and Measurement Equipment, Telecommunications Line Card, Medical Imaging Subsystem.
Standalone FPGA Configuration Storage
The EPC1LC20-WCEC52 stores the 1-Mbit configuration bitstream for SRAM-based Altera FPGAs and serially loads it during power-up via the PS configuration mode. With 1,048,576 bits of OTP storage and an 8 MHz DCLK, it can program a Cyclone or APEX device in roughly 130 ms. The 20-PLCC through-hole package fits legacy industrial backplanes where socketed PROMs simplify in-field bitstream rotation without surface-mount rework.
Recommended
Legacy Industrial Control Board
Long-lifecycle industrial controllers often retain the original Altera EPC1 design for 15+ years of field service. The EPC1LC20-WCEC52's 20-PLCC socketable form allows plant technicians to swap PROMs without reballing or hot-air rework. Its 3.3 V operation and 5.0 V tolerant I/O interface cleanly to both 3.3 V and 5.0 V FPGA rails common in industrial PLCs and motor-drive controllers.
Recommended
JTAG-Programmable Development Board
Engineering development kits for Cyclone and ACEX FPGAs typically include a JTAG chain with the EPC1LC20-WCEC52 attached. The on-board IEEE 1149.1 boundary-scan port enables engineers to program the OTP cells via USB-Blaster or ByteBlaster cables after PCB assembly, simplifying the bring-up workflow. Because the device is OTP, the final production bitstream is locked in only after the design is fully verified, preventing accidental field re-programming.
Recommended
Avionics and Defense Retrofit
Retrofit programs for military and aerospace electronics must maintain form, fit, and function with the original BOM. The EPC1LC20-WCEC52's 20-PLCC through-hole footprint and OTP behavior satisfy legacy FFF requirements where soldering a modern SOIC replacement would require a new PCB. Industrial temperature grade (-40C to +85C) and proven Altera silicon make it a qualified component for long-life avionics platforms.
Recommended
Test and Measurement Equipment
Bench-top instruments such as logic analyzers, oscilloscopes, and protocol testers often embed an Altera FPGA controlled by an EPC1 configuration PROM. The 20-PLCC socket allows service centers to swap a corrupted PROM in minutes rather than hours of board-level rework. With 1 Mbit of storage, the EPC1LC20-WCEC52 comfortably fits the bitstream of mid-density Cyclone and APEX devices used in high-speed acquisition paths.
Recommended
Telecommunications Line Card
Legacy telecom line cards based on Stratix or APEX FPGAs use the EPC1LC20-WCEC52 to store the configuration image during card insertion. Its 3.3 V supply aligns with telecom power rails and the 5.0 V tolerant I/O safely interfaces with 5 V FPGA banks during configuration. The OTP behavior guarantees that a corrupted remote firmware push cannot permanently rewrite the boot image, an important defense-in-depth property for carrier networks.
Recommended
Medical Imaging Subsystem
Medical imaging carts and portable ultrasound systems embed Altera Cyclone FPGAs configured by the EPC1LC20-WCEC52. The 20-PLCC through-hole socket simplifies in-field bitstream rotation when a device receives regulatory-approved software updates. Industrial temperature grade and Altera's mature silicon process deliver the long-term reliability expected by IEC 60601-compliant medical equipment manufacturers.
Recommended
Recommended Products Summary
Engineering reference data for EPC1LC20-WCEC52 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC1LC20-W | EPC1LC120 | EPC1L20 | EPC1441LC20 | EPC1L120 |
|---|---|---|---|---|---|---|---|
| Package | 20-PLCC | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same | 20-PLCC - same |
| Brand | Altera | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Memory Density | 1 Mbit | 1 Mbit | 1 Mbit | 1 Mbit | 1 Mbit | 0.4 Mbit | 1 Mbit |
| Configuration Clock (DCLK) | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Programming Type | OTP (JTAG ISP) | OTP (JTAG ISP) | OTP (JTAG ISP) | OTP (JTAG ISP) | OTP (JTAG ISP) | OTP (JTAG ISP) | OTP (JTAG ISP) |
| Configuration Protocol | Altera PS mode | Altera PS mode | Altera PS mode | Altera PS mode | Altera PS mode | Altera PS mode | Altera PS mode |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 20-PLCC socketable through-hole footprint for legacy retrofit (vs EPCQ64A (16-SOIC, surface-mount))
- OTP behavior prevents accidental field re-programming (vs EPC2 (reprogrammable))
- Built-in IEEE 1149.1 JTAG ISP eliminates pre-programming (vs Discrete parallel PROMs requiring pre-programming)
Design Notes
The EPC1LC20-WCEC52 is OTP - the JTAG ISP path performs the one and only programming operation and cannot be re-erased. Engineers sometimes mistakenly attempt a second JTAG cycle on a programmed device, which fails silently. Lock the bitstream version into your PLM (product lifecycle management) system and verify the blank device before mounting; once programmed, replacement requires a new PROM.
Place a 0.1 uF decoupling capacitor within 5 mm of the VCC pin and a bulk 10 uF tantalum or ceramic on the supply rail. CONF_DONE and nSTATUS are open-drain outputs that require external pull-up resistors (typically 4.7 kohm to the FPGA VCCIO rail). Keep the JTAG trace lengths matched within 25 mm to avoid boundary-scan timing violations.
DCLK and DATA must be length-matched within 10 mm for reliable configuration at the 8 MHz maximum rate. Series-terminate DCLK at the source with 33 ohm if the trace exceeds 50 mm. Avoid routing DCLK adjacent to switching power nodes; the JTAG state machine can misinterpret coupled noise as configuration data and lock up the FPGA.
Compliance Information
RoHS, REACH, lead-free and halogen-free status for EPC1LC20-WCEC52 is not published in the verified distributor snippets as of 2026-09-11. Contact Intel FPGA support or request a material declaration from the distributor for compliance documentation.
