EPC1L120 - Altera/Intel Configuration Device 120 kbit Serial | PLCC-20
MPN: EPC1L120 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.95 | $995.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.2 | $7,200.00 |
EPC1L120 Overview
A configuration device is a non-volatile serial memory specifically engineered to hold FPGA/CPLD configuration bitstreams and to manage the configuration sequence (nCONFIG, nSTATUS, CONF_DONE) on power-up. Compared to a generic serial EEPROM or flash, a configuration device handles the FPGA handshaking protocol, supplies data through the dedicated serial data line, and resets the FPGA automatically; it sits in the system hierarchy at configuration memory -> programmable-logic support -> memory IC -> integrated circuit. The EPC1 family belongs to Altera's classic configuration IC lineup introduced alongside the FLEX 6000 and FLEX 8000 series.
Key features of the EPC1L120 include 120 kbit user-configurable memory capacity, a 3.3 V or 5 V operating supply with MultiVolt output compatibility to drive 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V target devices, in-system programmability through an IEEE Std 1149.1 JTAG interface, and a low-pin-count serial interface that minimizes board space. The device is reprogrammable up to 100 times, supports cascaded configuration chains for multiple FPGAs, and offers separate JTAG and serial configuration ports.
Architecturally, the EPC1L120 integrates a CMOS serial EEPROM array, charge-pump high-voltage generator, JTAG TAP controller, and Altera's proprietary configuration control logic on a single die. The MultiVolt output driver uses an open-drain topology with an external pull-up resistor, allowing the same device to configure FPGAs of any I/O voltage on the same board.
Typical applications include storing the configuration bitstream for Altera FLEX 6000, FLEX 8000, MAX 7000S/A/B, and MAX 9000 devices; ISP-capable designs that allow remote field upgrade of logic; and multi-FPGA designs where configuration devices are cascaded. The PLCC-20 through-hole package also makes it suitable for prototype boards and legacy systems.
When designing with the EPC1L120, ensure the JTAG chain length does not introduce signal-integrity problems and that the open-drain CONF_DONE line has a proper pull-up to the target supply. Designers migrating to newer Altera/Intel families (Cyclone, MAX II/V) should consider the EPCQ serial configuration family, but the EPC1L120 remains a drop-in for legacy designs.
Drop-in alternatives for EPC1L120 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1L120 (same form factor and footprint) — differing in Memory Type, Package, Mounting Type, Interface, Memory Size.
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View Datasheet →EPC1L120 Maximum Ratings & Electrical Characteristics
| Memory Type | Configuration EEPROM |
| Memory Capacity | 120 kbit |
| Interface Type | Serial (Altera configuration protocol) |
| Operating Supply Voltage | 3.3 V / 5 V |
| Output Compatibility | MultiVolt: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V |
| Programmability | In-System via JTAG (IEEE 1149.1) |
| JTAG Support | Yes (dedicated JTAG port) |
| Package | PLCC-20 |
| Mounting Type | Surface Mount / Through-Hole (socket) |
| Reprogram Cycles | 100 cycles typical |
| Operating Temperature | -40C to +85C (industrial) |
| Compatible Altera FPGAs | FLEX 6000, FLEX 8000, MAX 7000, MAX 9000 families |
| Cascade Support | Yes (multi-FPGA configuration chains) |
EPC1L120 Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | nCONFIG — Configuration control input from FPGA |
| Pin 4 | nSTATUS — Status output to FPGA |
| Pin 5 | CONF_DONE — Configuration-done output to FPGA (MultiVolt open-drain) |
| Pin 6 | VCC — Power supply (3.3 V or 5 V) |
| Pin 7 | GND — Ground |
| Pin 8 | TCK — JTAG test clock input |
| Pin 9 | TMS — JTAG test mode select input |
| Pin 10 | TDI — JTAG test data input |
| Pin 11 | TDO — JTAG test data output |
| Pin 12 | OE/nCE — Output enable / chip enable |
| Pin 13 | nCASC — Cascade output for multi-device configuration chains |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | VCC — Power supply (3.3 V or 5 V) |
Typical Applications
EPC1L120 is suitable for 6 applications: Legacy Altera FLEX 6000 FPGA Configuration, MAX 7000 CPLD Bitstream Storage, Multi-FPGA Cascade Configuration, Industrial Control Systems with ISP Upgrade, Legacy Telecom Backplane Designs, Prototype and Educational FPGA Boards.
Legacy Altera FLEX 6000 FPGA Configuration
The EPC1L120 stores the configuration bitstream for Altera FLEX 6000 family FPGAs (EPF6010, EPF6016, etc.) in a single PLCC-20 footprint. Its 120 kbit capacity is sized to match the FLEX 6000 bitstream, while MultiVolt output drives the FPGA's 2.5 V or 3.3 V configuration pins directly. Compared to using a generic serial EEPROM, the EPC1L120 handles the nCONFIG/nSTATUS/CONF_DONE handshaking automatically, removing the need for external sequencer logic. ISP via JTAG allows field upgrades without removing the FPGA from the board.
Recommended
MAX 7000 CPLD Bitstream Storage
Altera MAX 7000S, MAX 7000A, and MAX 7000B CPLDs (EPM7128S, EPM7192S, etc.) can be configured from the EPC1L120 in JTAG ISP mode. The MultiVolt output matches the MAX 7000's 5 V tolerant configuration interface, and the JTAG chain can be shared between the CPLD and the configuration device for unified test access. The 120 kbit capacity covers most MAX 7000 designs, eliminating the need for parallel EPROM-based configuration. Compared to a discrete EEPROM solution, the EPC1L120 saves 8-12 board components and reduces PCB area.
Recommended
Multi-FPGA Cascade Configuration
Multiple EPC1L120 devices can be cascaded in a chain to configure two or more FPGAs simultaneously, using the nCASC pin to hand off configuration between devices. This topology is used in telecom backplane designs where multiple FLEX 8000 devices must come up in lock-step. The 120 kbit capacity supports one large FLEX 8000 (EPF8282, EPF8452) or several smaller FPGAs in the cascade. The PLCC-20 package provides mechanical robustness for industrial backplane environments where vibration is a concern.
Recommended
Industrial Control Systems with ISP Upgrade
The EPC1L120's JTAG ISP capability enables remote firmware upgrades in industrial PLC and motor control systems where the FPGA must be reconfigured in the field without opening the enclosure. Combined with a watchdog and security lock bits, the EPC1L120 supports controlled in-system updates over a JTAG boundary-scan controller. The -40C to +85C industrial temperature range and PLCC-20 package suit the harsh thermal and mechanical environment of factory-floor equipment. Compared to flash-based alternatives, the 100-reprogram cycle limit is acceptable for typical maintenance upgrade scenarios.
Recommended
Legacy Telecom Backplane Designs
Telecom equipment designed around 1998-2005 frequently pairs the EPC1L120 with FLEX 8000 FPGAs for protocol handling and glue logic. The PLCC-20 socketed package enables board-level replacement in field service depots, and the MultiVolt output allows the configuration device to drive 3.3 V FPGAs on the same backplane as 5 V legacy ASICs. The 120 kbit capacity matches the FLEX 8282/8452A bitstream size, eliminating split bitstream overhead. Compared to socketed EPROM-based configuration, the EPC1L120 reduces the configuration pin count and saves board area on dense backplane cards.
Recommended
Prototype and Educational FPGA Boards
University and prototyping boards designed around the Altera FLEX 6000/8000 and MAX 7000 families use the EPC1L120 for onboard configuration because the PLCC-20 package is socketable, allowing students to swap bitstreams without hot-air rework. The JTAG interface connects to the Altera ByteBlaster or USB-Blaster download cables, supporting one-click bitstream loading from the Quartus design environment. The 120 kbit capacity is sufficient for typical coursework projects involving 32-64 macrocell CPLDs or small FPGAs. Compared to using flash memory, the EPC1L120 automates the configuration handshake, letting students focus on logic design.
Recommended
Recommended Products Summary
Engineering reference data for EPC1L120 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1L20 | EPC1PC8 | EPC1441PC8 | EPC1213PC8 | EPC144PC8 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Memory Capacity | 120 kbit | 20 kbit | 1 Mbit | 144 kbit | 12 kbit | 144 kbit |
| Operating Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes |
| MultiVolt Output | Yes (1.5 V - 5 V) | Yes | Yes | Yes | Yes | Yes |
| Cascade Support | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Last time buy | Last time buy | Last time buy | Last time buy | Last time buy | Last time buy |
Key Differentiators
- Larger memory capacity than EPC1L20 (vs EPC1L20)
- Optimized for legacy Altera protocol (vs EPC1PC8)
- MultiVolt output flexibility (vs EPC1441PC8)
Design Notes
The CONF_DONE pin is an open-drain output. An external pull-up resistor (typically 10 kohm) must be connected to the target FPGA's VCCIO supply, not to the EPC1L120 VCC. If the pull-up is omitted or connected to the wrong supply, the FPGA will not detect configuration completion and will fail to enter user mode. Always verify the pull-up voltage matches the FPGA's configuration-bank supply.
Keep the JTAG chain impedance-controlled. Place 10 kohm pull-ups on TCK, TMS, and TDI near the EPC1L120, and 10 kohm pull-up on nCONFIG and nSTATUS. The DCLK and DATA traces should be length-matched within 2 cm to avoid skew-induced configuration failures. Use a dedicated JTAG header or header-compatible footprint that accepts the Altera ByteBlasterMV or USB-Blaster download cable.
Do not confuse the EPC1L120 with EPCQ16 or EPCQ32. The EPC1 family uses the legacy Altera configuration protocol for FLEX/MAX 7000 devices, while the EPCQ family uses the modern serial protocol for Cyclone/MAX II/V devices. Substituting EPC1L120 for an EPCQ part, or vice versa, will cause configuration failure even though both are configuration memory ICs.
Compliance Information
Compliance data not present in verified distributor pages. Intel/Altera product environmental information should be consulted for specific date-code RoHS/REACH status. AEC-Q100 not applicable as this is a logic/memory support IC, not an automotive-grade device.
