EPC1LC20C - 1Mb FPGA Config Memory, 20-Pin LCC | Altera
MPN: EPC1LC20C ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.8 | $980.00 |
| 500 | $8.6 | $4,300.00 |
| 1,000 | $7.4 | $7,400.00 |
EPC1LC20C Overview
Configuration devices are non-volatile serial memories specifically architected to store FPGA bitstream data. An LCC (Leadless Chip Carrier) is a ceramic-surface-mount package with castellated edges that solder to PCB pads. The EPC1LC20C belongs to Altera's EPC1 family, which preceded the EPC2 and EPC4 generations and remains in production for legacy design support. The device integrates a 4-pin JTAG interface (TCK, TMS, TDI, TDO), a serial configuration clock output (DCLK), data output (DATA), and chip-select controls, forming a complete FPGA configuration solution that replaces external boot PROMs in legacy systems.
Key features include 1,048,576 bits of flash storage, in-system programmability through JTAG (IEEE 1149.1 Boundary Scan), cascading support for multiple FPGA chains via nCS and CS pins, and a 5.0V or 3.3V supply mode. The LCC-20 ceramic package provides hermeticity and wide temperature tolerance suitable for industrial, military, and aerospace applications where plastic packages would be unreliable.
The EPC1LC20C uses a serial-data architecture where the FPGA acts as the configuration master. On power-up the EPC1 outputs a configuration clock on DCLK and bitstream data on DATA, which the slave FPGA latches until its SRAM is fully loaded. Configuration time for the FLEX 10K family is approximately 50 ms. Cascading allows multiple EPC1 devices to load multiple FPGAs in daisy-chain fashion by tying nCS/CS in sequence.
Typical applications include legacy Altera FLEX 10K / ACEX 1K / APEX 20K series FPGA boot memory, industrial control boards, telecom infrastructure retrofits, and military/aerospace systems where hermetic ceramic packaging is mandatory. Newer Altera FPGA families (Cyclone, Stratix, Arria, Agilex) use EPCQ or EPCQ-L serial quad-mode configuration devices that are not pin-compatible with the EPC1LC20C.
When designing with the EPC1LC20C, ensure the JTAG chain order matches the expected FPGA-then-EPC sequence to prevent configuration lockups. Decoupling the VCC pin with a 100 nF ceramic capacitor placed within 5 mm of the package pad is recommended to suppress switching transients during flash programming.
Drop-in alternatives for EPC1LC20C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1LC20C (same form factor and footprint) — differing in Memory Type, Package, Mounting Type, Memory Size, Compatible FPGA Families.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC1LC20N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$8.4 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC1441LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
Contact for price
View Datasheet →EPC1213LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.4 / Unit
View Datasheet →EPC1LC20C Maximum Ratings & Electrical Characteristics
| Memory Type | Serial Configuration Flash |
| Memory Size | 1 Mbit (1,048,576 bits) |
| Configuration Clock (DCLK) | 8 MHz maximum |
| Interface | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) |
| Supply Voltage | 3.3 V or 5.0 V |
| Programmability | In-system via JTAG |
| Cascading Support | Yes (nCS, CS pins) |
| Package | 20-pin LCC (Leadless Chip Carrier) |
| Mounting Type | Surface Mount (ceramic) |
| Operating Temperature | -40C to +85C (industrial) |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K |
| JTAG Pins | TCK, TMS, TDI, TDO |
| Configuration Mode | Slave-serial (FPGA-master) |
| MSL Level | MSL3 (ceramic, floor life 168 hours) |
EPC1LC20C Pin Configuration
| Pin 1 | nCS — Active-low chip select (input) |
| Pin 2 | CS — Active-high chip select (input) |
| Pin 3 | VCC — Power supply (3.3V or 5.0V) |
| Pin 4 | DATA — Serial configuration data output |
| Pin 5 | DCLK — Configuration clock output |
| Pin 6 | TDI — JTAG test data input |
| Pin 7 | TMS — JTAG test mode select |
| Pin 8 | TCK — JTAG test clock |
| Pin 9 | TDO — JTAG test data output |
| Pin 10 | GND — Ground reference |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
Typical Applications
EPC1LC20C is suitable for 6 applications: FLEX 10K FPGA Boot Memory, ACEX 1K Series FPGA Configuration, APEX 20K Series Multi-FPGA Cascade, Industrial PLC and Motor Controller, Military and Aerospace Avionics, Legacy Telecom Infrastructure Retrofits.
FLEX 10K FPGA Boot Memory
The EPC1LC20C's 1 Mbit flash array and 8 MHz DCLK output are sized to load the complete configuration bitstream of FLEX 10K10 / 10K20 / 10K30 / 10K40 SRAM-based LUT devices within approximately 50 ms of power-up. Placed adjacent to the EPF10K FPGA with DCLK->DCLK, DATA->DATA, and nSTATUS/CONF_DONE handshakes, it eliminates the need for an external EPROM boot device. Unlike parallel PROMs, the EPC1LC20C's serial interface frees FPGA user-IO pins for application use and supports in-system re-programming via JTAG. The LCC-20 ceramic package withstands the industrial -40C to +85C range required for factory-floor PLCs and CNC controllers. Recommended companions: EPF10K10ATC100, EPF10K20TC144.
Recommended
ACEX 1K Series FPGA Configuration
Altera ACEX 1K family devices such as EP1K10, EP1K30, and EP1K50 all require an EPC1-class configuration memory and the EPC1LC20C's 1 Mbit capacity comfortably fits the largest ACEX 1K bitstreams. With DCLK clocking at 8 MHz and serial data streaming, the EPC1LC20C delivers the entire configuration in under 100 ms. Designers benefit from the EPC1LC20C's in-system JTAG programmability, allowing field firmware updates without removing the device from the board. The LCC-20 ceramic package is preferred over plastic alternatives in telecom base-station backplanes where elevated ambient temperatures are common. Recommended companions: EP1K30QC208, EP1K50QC208.
Recommended
APEX 20K Series Multi-FPGA Cascade
For APEX 20K board designs using two or more FPGAs in a multi-FPGA chain, the EPC1LC20C supports cascading through its nCS and CS chip-select pins. Tie nCS of the first EPC1LC20C to CS of the second; each device sequentially loads its FPGA's bitstream. The 8 MHz DCLK remains stable across the chain, ensuring deterministic configuration time. This architecture lets one EPC1LC20C load a small FLEX device while a second loads an APEX 20K400 in the same chain, sharing JTAG infrastructure. The LCC-20 ceramic package survives the vibration profile of mobile robotics and military vehicle electronics. Recommended companions: EP20K200EBC356, EP20K400EBC652.
Recommended
Industrial PLC and Motor Controller
Programmable Logic Controllers (PLCs) and AC motor drives based on FLEX 10K or ACEX 1K FPGAs use the EPC1LC20C for deterministic boot in noisy factory environments. The 20-pin LCC ceramic package handles continuous -40C to +85C operation and resists humidity ingress better than plastic SOIC alternatives. JTAG in-system programming allows production-line firmware updates and field re-flashing without disassembling the controller. The EPC1LC20C's 8 MHz DCLK ensures the PLC becomes operational within milliseconds of power-on, which is critical for safety-rated emergency-stop response. Recommended companions: EPF10K10ATC100, IR2181SPBF (half-bridge gate driver for motor control).
Recommended
Military and Aerospace Avionics
Defense and aerospace platforms require hermetic ceramic packaging for high-reliability applications, and the EPC1LC20C's LCC-20 ceramic package meets this requirement. The EPC1LC20C is widely used in legacy MIL-STD-1553 databus interfaces, radar signal pre-processors, and flight-control retrofits that pair FLEX 10K FPGAs with radiation-tolerant microprocessors. Its in-system JTAG programmability enables field firmware upgrades via standard test equipment. The wide -40C to +85C operating range and hermetic seal eliminate the moisture-induced failures that would plague plastic EPCS devices in unpressurized avionics bays. Recommended companions: EPF10K10ATC100, MIL-STD-1553 transceivers.
Recommended
Legacy Telecom Infrastructure Retrofits
Telecom switching systems deployed in the late 1990s and early 2000s that use FLEX 10K or ACEX 1K FPGAs require periodic hardware refresh to extend service life. The EPC1LC20C provides a form-fit-function replacement for original EPC1LC20 boot memories that have failed in service, without requiring a board redesign. Its serial 8 MHz DCLK matches the original timing budget, and the LCC-20 footprint is identical to legacy PCB pads. Telecom operators can keep central-office switches operational through 2030+ by stocking the EPC1LC20C as a verified long-term spare. Recommended companions: EPF10K10ATC100, FLEX 10K30A, telecom backplane interconnect.
Recommended
Recommended Products Summary
Engineering reference data for EPC1LC20C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1LC20 | EPC1LC20N | EPC2LC20 | EPC1441LC20 | EPC1213LC20 |
|---|---|---|---|---|---|---|
| Package | 20-pin LCC | 20-pin LCC - same | 20-pin LCC - same | 20-pin LCC - same | 20-pin LCC - same | 20-pin LCC - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Memory Capacity | 1 Mbit | 1 Mbit | 1 Mbit | 2 Mbit (+100%) | 446 Kbit (-57%) | 212 Kbit (-80%) |
| Configuration Clock (DCLK) | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz | 8 MHz |
| Operating Temperature | -40C to +85C | 0C to +70C (commercial only) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| JTAG Programming | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K | Same families | Same families | FLEX 10K up to 10K100, ACEX, APEX 20K | FLEX 10K10 only | FLEX 10K10, small ACEX 1K |
| Lifecycle Status (2026) | NRND | Obsolete | NRND | NRND | Obsolete | Obsolete |
| Approx. Single-Unit Price (USD, 2026) | 12.50 | 10.00 - 15.00 | 11.00 - 14.00 | 14.00 - 18.00 | 8.00 - 12.00 | 6.00 - 10.00 |
Key Differentiators
- Industrial temperature range with explicit 'C' suffix (vs EPC1LC20)
- Double the storage capacity for larger FPGAs (vs EPC1441LC20)
- Same-package footprint with cascading support (vs EPC1213LC20)
Design Notes
Place a 100 nF X7R ceramic decoupling capacitor within 5 mm of the EPC1LC20C VCC pin (pin 3) and a bulk 10 uF tantalum or aluminum-polymer capacitor within 25 mm. The LCC-20 ceramic package has low lead inductance, but the configuration DCLK output at 8 MHz generates sharp 2 ns edges that couple noise into nearby analog supplies. Keep the DATA and DCLK traces short and away from switching power inductors. The EPC1LC20C's LCC pads require careful solder-paste stencil design - use a 5-mil stencil for the rectangular castellation pads to avoid solder-bridging across the package edges.
The DCLK signal from the EPC1LC20C to the FPGA must be treated as a clock distribution trace: keep it short (under 50 mm), series-terminate with 33 ohm if the trace exceeds 25 mm, and avoid splitting DCLK to multiple FPGAs without a buffer. The DATA output drives a single FPGA in non-cascade mode, but in cascade configurations where one EPC1LC20C feeds two FPGAs, insert a 74LVC1G17 Schmitt-trigger buffer between the DATA pin and the second FPGA's DATA input to maintain edge integrity. TMS, TCK, TDI inputs to the EPC1LC20C must be pulled to a defined state (pull-up to VCC) when JTAG is not in use to prevent spurious configuration initiation.
Do not use the EPC1LC20C with Cyclone, Stratix, Arria, or Agilex FPGAs - those families require the EPCQ-L or EPCS-L series with serial-quad mode. Do not apply 5 V to the EPC1LC20C's JTAG pins when configured for 3.3 V operation; level-shifters are required if the JTAG host is 5 V. When programming the EPC1LC20C via JTAG, ensure the JTAG chain order is EPC1LC20C-then-FPGA (not FPGA-then-EPC) - reversing the order causes the FPGA to enter user-mode before the EPC1LC20C has finished programming, which corrupts subsequent boot attempts. Always issue the Altera 'Configure Device' command in Quartus before power-cycling the board.
Estimated: at VCC=3.3V, during active flash programming, the EPC1LC20C draws approximately 30 mA peak, dissipating ~0.1 W. The LCC-20 ceramic package has excellent thermal conductivity to the PCB but no dedicated thermal pad. For most configurations at room temperature this is acceptable, but in sealed enclosures above +60C ambient, the junction temperature can rise 8-12C, so derate by 5C per 10 mA of additional supply current if external logic shares the same VCC rail. No heatsink is required for normal configuration-storage operation.
Compliance Information
RoHS and REACH compliance not explicitly stated in verified web data; original Altera 2002-vintage datasheet pre-dates EU RoHS directive (2006). LCC-20 ceramic package is lead-bearing (typical for pre-RoHS ceramic components). AEC-Q100 not applicable - configuration memory is not subject to automotive IC stress-test qualification. Designers requiring RoHS-compliant configuration memory should select the EPCQ-L family.
