EPF10K10TC144-4N - 10K Gates FLEX-10K FPGA, 144-LQFP | Intel / Altera
MPN: EPF10K10TC144-4N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.95 | $249.50 |
| 100 | $21.4 | $2,140.00 |
| 500 | $18.25 | $9,125.00 |
| 1,000 | $15.5 | $15,500.00 |
EPF10K10TC144-4N Overview
What is an FPGA? An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement custom digital logic circuits by configuring an array of configurable logic blocks (CLBs/LABs), programmable interconnects, and I/O blocks. FPGAs sit in the hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA. The FLEX-10K family, introduced in the mid-1990s, was the industry's first family to embed dedicated SRAM array blocks (EABs) for on-chip memory, pioneering the modern concept of "System-on-a-Programmable-Chip" (SOPC) integration of logic and memory.
Key specifications include 6,144 typical gates / 10,000 maximum usable gates, 72 LABs each containing 8 logic elements (LEs) for 576 LEs total, 102 user I/Os, and a 4.75V-5.25V single-supply operating range. The "-4" speed grade offers faster propagation delay than the -3 / -2 grades for time-critical paths, and the device is rated for commercial temperature operation (0C to 70C). It is fabricated on a 0.42 micron CMOS process and supports in-system programmability via the Altera ByteBlaster or BitBlaster configuration interface.
Typical applications include legacy industrial control, communication backplane glue logic, telecom interface boards, PCI bus bridges, and ASIC prototyping where 5V tolerant I/O and mid-density logic capacity are required. The 144-LQFP footprint is widely supported on legacy through-hole and surface-mount PCB designs. Engineers migrating from the FLEX-10K family to modern Cyclone or MAX families should note the 5V VCC requirement differs from current 1.2V-3.3V FPGAs.
When designing with EPF10K10TC144-4N, observe the JTAG IEEE 1149.1 boundary-scan requirements, decoupling with 0.1 uF ceramic capacitors per VCC pin, and consider the configuration scheme (PS, PPS, AS, or JTAG) needed for the design. The device is supported by Altera legacy MAX+PLUS II and Quartus design software.
This page synthesizes distributor pricing, drop-in same-package alternatives from the FLEX-10K family, and practical design notes not consolidated in the original Altera datasheet. Pricing, stock, and specifications are last verified 2026-09-11 from authorized distributors.
Drop-in alternatives for EPF10K10TC144-4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPF10K10TC144-4N (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, RoHS Status, Typical Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF10K10TC144-3N
✅ Drop-In✓ In Stock
$17.85 / Unit
View Datasheet →EPF10K10TC144-3
✅ Drop-In✓ In Stock
$26.4 / Unit
View Datasheet →EPF10K10ATC144-3N
✅ Drop-In✓ In Stock
$24.75 / Unit
View Datasheet →EPF10K10ATI144-4
✅ Drop-In✓ In Stock
$8.2 / Unit
View Datasheet →EPF10K20TC144-4N
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EPF10K10TC144-4N Maximum Ratings & Electrical Characteristics
| Series | FLEX-10K |
| Device Family | FLEX-10K Embedded Programmable Logic Device |
| Logic Elements / Cells | 576 |
| Logic Array Blocks (LABs) | 72 |
| Total RAM Bits | 6144 |
| Number of Gates | 10000 (typical usable) |
| Number of I/O | 102 |
| Voltage Supply | 4.75 V to 5.25 V |
| Operating Temperature | 0 C to 70 C (Commercial) |
| Mounting Type | Surface Mount |
| Package | 144-LQFP (TQFP-144) |
| Speed Grade | -4 (fastest in FLEX-10K family) |
| Lead-Free | Yes (N suffix) |
| Process Technology | 0.42 micron CMOS |
| Configuration Interface | JTAG / PS / PPS / AS via ByteBlaster |
| RoHS Status | Compliant (N suffix) |
EPF10K10TC144-4N Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 2 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 3 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 4 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 5 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 6 | VCCINT — Core logic supply (5V) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 9 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 10 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 11 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 12 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 13 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 14 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 15 | TDI — JTAG Test Data Input |
| Pin 16 | TMS — JTAG Test Mode Select |
| Pin 17 | TCK — JTAG Test Clock |
| Pin 18 | VCCIO — I/O supply (5V) |
| Pin 19 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 20 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 21 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 22 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 23 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 24 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 25 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 26 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 27 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 28 | GND — Ground |
| Pin 29 | VCCINT — Core logic supply (5V) |
| Pin 30 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 31 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 32 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 33 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 34 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 35 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 36 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 37 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 38 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 39 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 40 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 41 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 42 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 43 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 44 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 45 | GND — Ground |
| Pin 46 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 47 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 48 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 49 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 50 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 51 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 52 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 53 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 54 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 55 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 56 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 57 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 58 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 59 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 60 | I/O — User I/O pin (bank 2) - bidirectional |
| Pin 61 | VCCINT — Core logic supply (5V) |
| Pin 62 | GND — Ground |
| Pin 63 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 64 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 65 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 66 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 67 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 68 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 69 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 70 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 71 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 72 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 73 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 74 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 75 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 76 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 77 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 78 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 79 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 80 | nCONFIG — Configuration control (active-low) |
| Pin 81 | nSTATUS — Configuration status (active-low) |
| Pin 82 | CONF_DONE — Configuration done |
| Pin 83 | DCLK — Configuration clock |
| Pin 84 | DATA0 — Configuration data input |
| Pin 85 | VCCIO — I/O supply (5V) |
| Pin 86 | GND — Ground |
| Pin 87 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 88 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 89 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 90 | I/O — User I/O pin (bank 3) - bidirectional |
| Pin 91 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 92 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 93 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 94 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 95 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 96 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 97 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 98 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 99 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 100 | VCCINT — Core logic supply (5V) |
| Pin 101 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 102 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 103 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 104 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 105 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 106 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 107 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 108 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 109 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 110 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 111 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 112 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 113 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 114 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 115 | GND — Ground |
| Pin 116 | VCCIO — I/O supply (5V) |
| Pin 117 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 118 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 119 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 120 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 121 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 122 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 123 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 124 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 125 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 126 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 127 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 128 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 129 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 130 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 131 | I/O — User I/O pin (bank 4) - bidirectional |
| Pin 132 | VCCINT — Core logic supply (5V) |
| Pin 133 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 134 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 135 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 136 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 137 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 138 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 139 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 140 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 141 | I/O — User I/O pin (bank 1) - bidirectional |
| Pin 142 | TDO — JTAG Test Data Output |
| Pin 143 | GND — Ground |
| Pin 144 | VCCIO — I/O supply (5V) |
Typical Applications
EPF10K10TC144-4N is suitable for 6 applications: Legacy Industrial Control Logic, Telecom Backplane Glue Logic, ASIC Prototyping Platform, PCI Bus Bridge and Peripheral Controller, Embedded Memory Subsystem Glue Logic, Test & Measurement Instrumentation.
Legacy Industrial Control Logic
The EPF10K10TC144-4N is widely deployed in legacy industrial control PLCs and process automation backplanes because its 5V TTL I/O directly interfaces to 5V sensors, optocouplers, and 5V CMOS peripherals without level shifters. The 10,000-gate capacity fits typical scan-engine plus glue-logic designs for machine controllers, and the 144-LQFP footprint supports standard SMT assembly lines that have been qualified over decades of high-reliability production. Engineers sustaining long-lifecycle equipment (15+ years in the field) leverage the -4 speed grade for deterministic timing on interrupt-handling state machines.
Recommended
Telecom Backplane Glue Logic
The EPF10K10TC144-4N's 102 user I/Os and 4.75V-5.25V supply tolerance map naturally to telecom backplane designs where 5V bus transceivers, framing logic, and TDM crossbar switching need to be bridged between legacy ASICs. The -4 speed grade supports E1/T1 line-rate glue logic at 2.048 Mbps / 1.544 Mbps with comfortable timing margins, and the FLEX-10K architecture provides deterministic pin-to-pin delays well-suited to synchronous bus implementations. As of 2026, this part remains in active service-class spares for installed telecom infrastructure where board redesign is prohibitively expensive.
Recommended
ASIC Prototyping Platform
The EPF10K10TC144-4N historically served as a low-cost ASIC prototyping vehicle for 5V CMOS ASIC designs, allowing engineers to validate control logic and state machines on a programmable die before committing to mask sets. With 576 logic elements and 102 I/Os, it covers the typical glue-logic footprint of an 8051 peripheral controller or HDLC protocol block, and ByteBlaster configuration enables rapid design iteration. Modern engineering teams still use NOS EPF10K10 parts to keep legacy ASIC-emulation test fixtures alive in defense and aerospace labs.
Recommended
PCI Bus Bridge and Peripheral Controller
The EPF10K10TC144-4N fits 32-bit PCI bridge and peripheral-controller designs operating at 33 MHz, where the 102 I/Os accommodate the 32-bit address/data bus plus control signals and a local peripheral bus. The -4 speed grade's propagation delay supports the 30 ns PCI bus cycle with comfortable margin, and 5V I/O compliance matches the original PCI electrical specification that required 5V signaling. Mainstream deployment was in industrial PCs, embedded single-board computers, and PCI-to-ISA bridge cards during the late 1990s through early 2000s.
Recommended
Embedded Memory Subsystem Glue Logic
The EPF10K10TC144-4N's 6,144 bits of embedded SRAM (via 2,048-bit EABs) allow it to implement small FIFOs, LUT-based register files, and protocol-header look-up tables directly alongside the logic fabric - the original System-on-a-Programmable-Chip concept. Designers use it to consolidate a discrete SRAM plus address-decoder pair into a single chip, saving board area in legacy compactPCI and VME designs. The 144-LQFP package remains hand-reworkable for field upgrades in defense electronics sustainment programs.
Recommended
Test & Measurement Instrumentation
The EPF10K10TC144-4N supports custom test-equipment designs where precise timing and 5V I/O matter - for example, JTAG-controlled boundary-scan controllers, oscilloscope trigger sequencers, and protocol analyzer front-ends. The -4 grade's deterministic timing avoids jitter in time-critical measurement paths, and 102 I/Os accommodate parallel test busses (HP-IB, VXI backplane, PXI). NOS inventory is still actively traded on the secondary market to sustain deployed ATE systems in calibration labs and depot-level repair facilities.
Recommended
Recommended Products Summary
Engineering reference data for EPF10K10TC144-4N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF10K10TC144-3N | EPF10K10TC144-3 | EPF10K10ATC144-3N | EPF10K10ATI144-4 | EPF10K20TC144-4N |
|---|---|---|---|---|---|---|
| Package | 144-LQFP (TQFP-144) | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same |
| Brand | Altera (Intel) | Altera - same | Altera - same | Altera - same | Altera - same | Altera - same |
| Speed Grade | -4 (fastest) | -3 (slower) | -3 (slower) | -3 (FLEX-10KA) | -4 (same) | -4 (same) |
| Logic Capacity | 10K gates / 576 LEs | 10K gates / 576 LEs (same) | 10K gates / 576 LEs (same) | 10K gates / 576 LEs (same) | 10K gates / 576 LEs (same) | 20K gates / 1152 LEs (double) |
| User I/O Count | 102 | 102 (same) | 102 (same) | 102 (same) | 102 (same) | 102 (same) |
| Lead-Free (RoHS) | Yes (N suffix) | Yes (N suffix) | No (SnPb finish) | Yes (N suffix) | No (no N suffix) | Yes (N suffix) |
| Operating Temperature | 0C to 70C (Commercial) | 0C to 70C (Commercial) | 0C to 70C (Commercial) | 0C to 70C (Commercial) | -40C to 85C (Industrial) | 0C to 70C (Commercial) |
| Voltage Supply | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V | 4.75V to 5.25V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest speed grade (-4) in the FLEX-10K family for time-critical paths (vs EPF10K10TC144-3N)
- Lead-free (N suffix) for RoHS compliance (vs EPF10K10TC144-4 (no N suffix))
- 102 I/O pins in 144-LQFP, balancing density with hand-reworkability (vs EPF10K10QC208-4N)
- 5V TTL I/O compliance without level shifters (vs EP1K10TC144-2N (FLEX-10KE))
Design Notes
The EPF10K10TC144-4N requires a single 5V supply (4.75V-5.25V) for both VCCINT (core) and VCCIO (I/O banks); unlike modern FPGAs there is no separate core voltage rail. Place one 0.1 uF ceramic decoupling capacitor within 5 mm of every VCC pin (the package has multiple VCCINT and VCCIO pins per the datasheet pinout), plus a single 10 uF tantalum or aluminum polymer bulk capacitor on each supply rail at the PCB edge connector. Estimated: at -4 speed grade with all 576 LEs toggling at 50 MHz, dynamic current draw can reach 150-200 mA, so the 5V regulator should source at least 500 mA per FPGA with adequate thermal margin.
Use a 4-layer PCB stackup with continuous ground and power planes directly under the 144-LQFP footprint to minimize SSO (simultaneous-switching-output) noise, which is significant on a 5V FPGA with 102 outputs. The 144-LQFP has 0.5 mm pitch leads; follow JEDEC MS-026 land-pattern recommendations with 0.27 mm wide pads and 0.6 mm length. Add guard traces around critical clock inputs (DCLK, TCK) to prevent crosstalk from adjacent user I/O toggling at high frequency. Estimated: SSO can induce 200-400 mV of ground bounce on a poorly-decoupled board.
Series-terminate all high-speed outputs driving traces longer than 50 mm with a 33 ohm resistor placed within 10 mm of the FPGA pin to dampen reflections on the 5V TTL signaling. The -4 speed grade has typical edge rates of 1-2 ns, which combined with the 5V swing produces significant transmission-line effects on unterminated traces. JTAG signals (TCK, TMS, TDI, TDO) should be guarded-traced and pulled up per the FLEX-10K datasheet to prevent spurious configuration entry during power-up.
Do not confuse the EPF10K10TC144-4N with the EPF10K10TC144-3N (-3 speed grade) or EPF10K10ATC144-3N (FLEX-10KA architecture) - all three share the same 144-LQFP footprint and pinout, but bitstreams are NOT interchangeable due to internal timing-architecture differences between FLEX-10K and FLEX-10KA. When sustaining legacy designs, double-check the exact suffix on incoming parts; broker/NOS channels have shipped mislabeled -4/-3 parts in the past. Also verify VCCIO is tied to 5V, not 3.3V, since the I/O banks are not 3.3V tolerant.
Compliance Information
RoHS compliant by N suffix per Altera product specifications. Reach compliance assumed for lead-free finish but not explicitly stated in datasheet snippet. AEC-Q100 not applicable for this commercial-grade FPGA. Halogen-free status not specified in provided data.