EPM5064LC-1 - 64-Macrocell 5V CPLD, 44-Pin PLCC | Altera
MPN: EPM5064LC-1 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EPM5064LC-1 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays on a single die, connected by a central Programmable Interconnect Array (PIA). The MAX 5000 family is one of Altera's earliest CPLD generations and sits in the hierarchy: CPLD -> programmable logic -> logic IC -> integrated circuit. CPLDs are used where deterministic pin-to-pin propagation delay, simple HDL synthesis, and instant-on non-volatile configuration are required - typically replacing dozens of 74-series logic chips on a board.
Key features of the EPM5064LC-1 include 4 Logic Array Blocks (LABs) interconnected through the PIA, a worst-case propagation delay of approximately 40 ns through the device (tPD1), 36 input lines feeding 7 dedicated inputs that can also serve clock functions, and 28 output lines with macrocell-level register/bypass control. The IC is specified for commercial 5 V operation with a supply range of 4.75 V to 5.25 V, and supports in-system programming via JTAG.
The MAX 5000 architecture uses an EEPROM/EPROM cell array for the AND plane and a fixed OR plane feeding each macrocell's flip-flop, giving the part its well-known deterministic timing advantage over SRAM-based FPGAs. Designers use the device with Altera's legacy MAX+PLUS II toolchain (or modern Quartus with legacy device support) to compile AHDL, VHDL, or Verilog designs into the JEDEC fuse map.
Typical applications for the EPM5064LC-1 include 5V bus-interface address decoding, legacy ISA/PCI adapter glue logic, custom state-machine controllers, bus-width adapters, and pin-compatible upgrades for older discrete TTL designs. It is also a popular choice for industrial control boards where non-volatile, instant-on logic is essential and the design will not be re-programmed in the field.
When designing with the EPM5064LC-1, confirm the supply voltage matches the 4.75-5.25 V range and add a 0.1 uF decoupling capacitor near each VCC pin to handle the simultaneous-switching output current spikes. Note that the -1 speed grade is the slowest bin (12 ns / 40 ns tPD); if your design needs higher throughput, look at the EPM5064LC-2 (faster grade, same die/package) before changing footprint.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPM5064LC-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM5064LC-1 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Process Technology, Usable Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5064LC
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EPM5064LC-2
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →EPM5064JI-1
✅ Drop-In✓ In Stock
$3.4 / Unit
View Datasheet →EPM5064JC
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EPM5064JC-1
✅ Drop-In✓ In Stock
$18.25 / Unit
View Datasheet →EPM5064JC-2
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →EPM5064LC-1 Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Macrocells | 64 |
| Logic Array Blocks (LABs) | 4 |
| Usable Gates | 1.25K (approx.) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Internal Operating Frequency | 62.5 MHz |
| Propagation Delay (tPD) | 40 ns |
| Input Lines | 36 |
| Dedicated Inputs | 7 |
| Output Lines | 28 |
| Programming Technology | OTP / UV-Erasable EPROM |
| Package | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | CMOS |
| Programming Interface | JTAG (ByteBlaster-compatible) |
EPM5064LC-1 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 18 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 19 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 20 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 21 | VCC — +5V supply |
| Pin 22 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 23 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 24 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 25 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 26 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 27 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 28 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 29 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 30 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 33 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 34 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 35 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 36 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 37 | I/O — Bidirectional I/O pin (macrocell) |
| Pin 38 | TDI — JTAG Test Data In (programming) |
| Pin 39 | TMS — JTAG Test Mode Select (programming) |
| Pin 40 | TCK — JTAG Test Clock (programming) |
| Pin 41 | TDO — JTAG Test Data Out (programming) |
| Pin 42 | OE1 — Global Output Enable (dedicated) |
| Pin 43 | CLK1 — Global Clock (dedicated input) |
| Pin 44 | VCC — +5V supply |
Typical Applications
EPM5064LC-1 is suitable for 6 applications: 5V Bus Address Decoding, Legacy ISA / PCI Adapter Glue Logic, Custom State-Machine Controllers, Bus-Width Adapters and Level Shifters, Pin-Compatible Upgrade of Discrete TTL Logic, Industrial Control and Instrumentation Front-Ends.
5V Bus Address Decoding
The EPM5064LC-1 is well-suited for 5V address-decoding glue logic on ISA, VME, and legacy PCI adapter boards, where its 64 macrocells and 28 output lines can replace multiple 74LS138 / 74LS139 decoder trees while adding custom chip-select equations. With 4.75-5.25V VCC tolerance and TTL-compatible outputs, it interfaces directly to 5V microprocessors and peripheral buses. The 40 ns tPD at the -1 speed grade provides one to two clock cycles of decoding latency in 25 MHz systems. Designers can fold wait-state generators and byte-steering logic into the same device, reducing board area and improving noise margins versus discrete gates.
Recommended
Legacy ISA / PCI Adapter Glue Logic
Inserted between a legacy host bus and peripheral ASICs, the EPM5064LC-1 handles bus-cycle control, byte enables, parity generation, and interrupt steering in a single non-volatile device. Its deterministic 40 ns propagation delay (LC-1) is well-matched to 8 MHz ISA timing and to custom 33 MHz local-bus implementations. OTP / UV-erasable programming means the design is locked at production - ideal for shipping adapters that will never be reconfigured in the field. The 44-pin PLCC socket-mount package also supports easy prototyping and field replacement on legacy industrial boards.
Recommended
Custom State-Machine Controllers
Designers implement Moore and Mealy state machines in the EPM5064LC-1 using its 64 macrocell flip-flops and AND/OR programmable logic array, achieving deterministic state transitions with predictable timing. The 62.5 MHz internal frequency and 40 ns tPD at LC-1 make it suitable for controller state machines running at system clocks up to ~20 MHz. Compared to a microcontroller, the CPLD offers instant-on, zero-software, and glitch-free deterministic state transitions - critical in motor-control, sequencing, and safety-interlock applications. The OTP architecture also prevents firmware tampering in deployed industrial equipment.
Recommended
Bus-Width Adapters and Level Shifters
The EPM5064LC-1 frequently appears in 8-to-16 bit and 16-to-32 bit bus-width adapters, where its 36 inputs and 28 outputs give ample headroom for multiplexers, transceivers, and control logic. When paired with external 74-series transceivers, it implements direction-control and enable sequencing without a microcontroller. At 5V VCC with TTL I/O it integrates directly into 5V-only legacy boards. The 44-pin PLCC also fits the same socket footprint as several MAX 7000AE devices, easing migration paths when more logic capacity is later required.
Recommended
Pin-Compatible Upgrade of Discrete TTL Logic
The EPM5064LC-1 in 44-pin PLCC is often used to consolidate tens of 74LS/74F gates, multiplexers, and flip-flops onto a single programmable device, shrinking board area and BOM cost on legacy designs. Because the part is non-volatile and instant-on, it boots into a known state with no external configuration memory. Compared to equivalent discrete-TTL implementations, the CPLD reduces power consumption by 30-60% on typical glue-logic functions. Engineers targeting modern revisions can move to the MAX II or MAX V families, but the LC-1 remains the lowest-cost option for retrofits of working legacy hardware.
Recommended
Industrial Control and Instrumentation Front-Ends
In industrial control and instrumentation front-ends, the EPM5064LC-1 handles digital signal conditioning, sensor-multiplexer addressing, and front-panel scan-logic. Its deterministic timing and OTP non-volatility suit safety-critical and locked-firmware deployments. Combined with external 5V op-amps and ADCs, the CPLD becomes the digital backbone of the front-end, replacing 4-6 discrete MSI TTL packages. Industrial users should specify the EPM5064JI-1 (industrial temperature grade) for -40 to +85C environments; the LC-1 is limited to commercial 0 to +70C operation.
Recommended
Recommended Products Summary
Engineering reference data for EPM5064LC-1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5064LC | EPM5064LC-2 | EPM5064JI-1 | EPM5064JC | EPM5064JC-1 | EPM5064JC-2 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 44-pin PLCC | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same | 44-pin PLCC - same |
| Macrocells | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Speed Grade | -1 (slowest) | unspecified / base | -2 (faster) | -1 (industrial temp) | unspecified / base | -1 (windowed) | -2 (windowed, faster) |
| Programming Technology | OTP / UV-Erasable (LC) | OTP / UV-Erasable | OTP / UV-Erasable | OTP / UV-Erasable | Windowed UV-Erasable (ceramic) | Windowed UV-Erasable (ceramic) | Windowed UV-Erasable (ceramic) |
| Temperature Grade | Commercial (0 to +70C) | Commercial | Commercial | Industrial (-40 to +85C) | Commercial (ceramic) | Commercial (ceramic) | Commercial (ceramic) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Lowest-cost 64-macrocell 5V CPLD in 44-pin PLCC (vs EPM7032AE)
- Industrial temperature option in same footprint (vs EPM5064JI-1)
- Faster speed grade available on same die (vs EPM5064LC-2)
Design Notes
The EPM5064LC-1 requires a regulated 5 V supply within 4.75 V to 5.25 V. Place a 0.1 uF ceramic decoupling capacitor near every VCC pin (pin 21 and pin 44) and a bulk 10-47 uF electrolytic or tantalum at the board's 5 V entry point. Simultaneous-switching output current spikes on the 28 output lines can momentarily sag VCC, so a low-impedance power plane is recommended for designs that toggle many outputs in parallel.
The EPM5064LC-1 is OTP / UV-erasable, not in-system reprogrammable: once programmed in a plastic package, the device cannot be erased. Use a windowed ceramic package (JC grade) for design iteration and switch to LC only for production. Also note that the MAX 5000 family predates JTAG boundary-scan for all pins - rely on functional test rather than boundary-scan for production board test.
Keep the JTAG chain short (TCK/TMS/TDI/TDO on pins 38-41). At 40 ns tPD, the device's worst-case pin-to-pin delay is well below typical 8 MHz ISA timing, but long output traces (>5 cm) without series damping may produce ringing on heavily-loaded buses. Add 22-33 ohm series resistors on clock and chip-select outputs when driving long backplane traces.
Estimated: with 28 outputs at 4 mA DC load and 5V VCC, internal dissipation is approximately 0.5-0.8 W under typical switching activity. The 44-pin PLCC has a junction-to-ambient thermal resistance of roughly 50-60 C/W, giving a 25-40 C rise above ambient. No heatsink is required, but provide adequate airflow if the part is mounted near a heat source or in a fully sealed enclosure.
Compliance Information
RoHS / lead-free status for the original EPM5064LC-1 was not present in the verified web data; original MAX 5000 family parts from Altera's 1990s product line are commonly non-RoHS (SnPb finish) and may require the JC or LC lead-free variants when compliance is required.
