EP910LC44-40 - 24-Macrocell Classic EPLD, 44-Pin PLCC | Intel / Altera
MPN: EP910LC44-40 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910LC44-40 Overview
What is an EPLD? An Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that uses EPROM/EEPROM storage cells to retain the user's logic configuration. EPLDs sit in the hierarchy: programmable logic -> PLD -> EPLD -> CMOS PLD -> programmable logic device -> semiconductor IC. The Classic EPLD family preceded modern CPLDs in Altera's roadmap, offering a CMOS PAL-type architecture with sum-of-products logic and a fixed AND-to-OR interconnect. EPLDs are typically used for glue logic, address decoding, bus interfacing, state-machine implementation, and peripheral control where deterministic 40 ns timing is acceptable and in-system reprogrammability is not required.
Key features of the EP910LC44-40 include 24 macrocells, 240 product terms, 24 bidirectional I/O pins, 12 dedicated input pins, 2 global clock inputs, and TTL-compatible I/O. The device supports 100% TTL-level compatibility and operates from a single 5 V supply. Logic is configured via industry-standard JEDEC maps and may be programmed using Altera's legacy LP6, MP9, or third-party programmers; UV-erasable variants (windowed ceramic DIP/CLCC packages) coexist with one-time-programmable plastic packages in the same family. Architectural enhancements such as programmable macrocell flip-flops and configurable I/O architectures distinguish the Classic family from earlier PAL/GAL devices.
Architecturally, the EP910LC44-40 uses a programmable AND array feeding a fixed OR array, with each macrocell containing a flip-flop, output enable, and feedback path. The 2 dedicated clock pins drive the global clock network that fans out to every macrocell flip-flop, while the 24 I/O pins can be individually configured as input, output, or bidirectional. Power consumption is reduced by CMOS technology compared with bipolar PAL parts, and the device operates across the commercial 0C to +70C temperature range. Programming is non-volatile in windowed packages, enabling multiple design iterations via UV erasure.
Typical applications include legacy industrial control boards, address decoding for microprocessor/microcontroller systems, peripheral interface glue logic, bus arbitration circuits, and replacement of discrete 74LS/74F TTL logic. Engineers also deploy the EP910 in aerospace and defense sustainment programs, medical equipment long-life-cycle boards, and test & measurement instrumentation where original designs must be maintained for 20+ year product support windows. The 44-pin PLCC package is socket-compatible with production programmers and is footprint-compatible with other PLCC-44 EPLDs in the Classic family.
When designing with the EP910LC44-40, note that propagation delay of 40 ns may not meet timing budgets in modern 33 MHz or faster microprocessors; verify setup/hold timing against the asynchronous or synchronous interface requirements. The device must be programmed before use with a JEDEC file generated by MAX+PLUS II (legacy) or compatible tools; designs not following the macrocell product-term limits must be recompiled for the target device. The plastic PLCC package is one-time programmable in non-windowed variants, so plan JTAG-free programming flow during manufacturing.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single-decision reference for legacy EPLD procurement.
Drop-in alternatives for EP910LC44-40 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC44-40 (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Architecture, Programming Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC44-35
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →EP910LC44-30T
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP910LC44
✅ Drop-In✓ In Stock
$8.95 / Unit
View Datasheet →EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910LC-40T
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP910LC44-40 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Macrocells | 24 |
| Product Terms (Total) | 240 |
| I/O Pins | 24 (bidirectional) |
| Dedicated Inputs | 12 |
| Total Inputs | 36 |
| Global Clock Inputs | 2 |
| Propagation Delay (tPD) | 40 ns |
| Supply Voltage (VCC) | 5 V (nominal) |
| Technology | CMOS, UV-erasable EPROM |
| Logic Compatibility | TTL-compatible I/O |
| Package | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Operating Temperature | 0C to +70C (commercial) |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer |
| Mounting Type | Surface Mount |
EP910LC44-40 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell 16) |
| Pin 18 | I/O — Bidirectional I/O pin (macrocell 17) |
| Pin 19 | I/O — Bidirectional I/O pin (macrocell 18) |
| Pin 20 | I/O — Bidirectional I/O pin (macrocell 19) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — Bidirectional I/O pin (macrocell 20) |
| Pin 23 | I/O — Bidirectional I/O pin (macrocell 21) |
| Pin 24 | I/O — Bidirectional I/O pin (macrocell 22) |
| Pin 25 | I/O — Bidirectional I/O pin (macrocell 23) |
| Pin 26 | I/O — Bidirectional I/O pin (macrocell 24) |
| Pin 27 | IN — Dedicated input |
| Pin 28 | IN — Dedicated input |
| Pin 29 | IN — Dedicated input |
| Pin 30 | IN — Dedicated input |
| Pin 31 | IN — Dedicated input |
| Pin 32 | IN — Dedicated input |
| Pin 33 | IN — Dedicated input |
| Pin 34 | IN — Dedicated input |
| Pin 35 | IN — Dedicated input |
| Pin 36 | IN — Dedicated input |
| Pin 37 | IN — Dedicated input |
| Pin 38 | CLK1 — Global clock input 1 |
| Pin 39 | CLK2 — Global clock input 2 |
| Pin 40 | VCC — +5 V supply |
| Pin 41 | VCC — +5 V supply |
| Pin 42 | VCC — +5 V supply |
| Pin 43 | VCC — +5 V supply |
| Pin 44 | VCC — +5 V supply |
Typical Applications
EP910LC44-40 is suitable for 6 applications: Microprocessor Address Decoding, Industrial Glue Logic Replacement, Legacy Aerospace & Defense Sustainment, Medical Equipment Long-Life-Cycle Boards, Test & Measurement Instrumentation, Bus Arbitration and Peripheral Control.
Microprocessor Address Decoding
The EP910LC44-40 is well-suited for 8-bit and 16-bit microprocessor address decoding in legacy embedded systems where the 40 ns tPD aligns with standard peripheral access times. Its 24 dedicated macrocells can implement complex chip-select logic with multiple address-strobe combinations (A0-A23 plus /RD, /WR, /MREQ, /IOR, /IOW), while the 24 bidirectional I/O pins allow direct bus interface without external buffers. The non-volatile CMOS EPROM configuration means the decoder is programmed once at board build and retains logic without a configuration PROM. Compared to discrete 74LS138/74LS139 decoder trees, the EPLD reduces board area by ~70% and simplifies BOM management. The 5 V TTL-compatible interface drops directly into 8086, 68k, Z80, and 8051-family designs.
Recommended
Industrial Glue Logic Replacement
Industrial control boards originally built with discrete 74LS, 74F, or 74HC TTL logic benefit from the EP910LC44-40 by consolidating multiple SSI/MSI gates into a single programmable device. The 240 product terms and 24 macrocells replace approximately 8-12 standard 20-pin PAL/GAL devices or 30-50 discrete TTL packages. The 40 ns propagation delay is well-matched to legacy PLC backplanes, sensor interfaces, and motor-control logic at sub-1 MHz clock rates. Industrial temperature variants (EP910LI44-40) extend operation to -40C to +85C for harsh factory environments. Engineers should budget for legacy Altera MAX+PLUS II development tools and a JEDEC-compatible programmer.
Recommended
Legacy Aerospace & Defense Sustainment
Aerospace and defense programs with 20+ year sustainment windows (e.g., avionics LRUs, naval systems, ground radar) often require the EP910LC44-40 as a form-fit-function replacement for original Altera designs still in service. The PLCC-44 package and pinout match older board layouts exactly, enabling drop-in replacement without PCB rework. Franchised distributors like Rochester Electronics supply traceable, date-coded parts with Certificates of Conformance for DO-254 and MIL-STD-810 compliance documentation. Designers must verify tPD margins against current mission profiles, as the 40 ns grade may require derating in -55C cold-start scenarios; the -30 or -35 grade provides additional timing headroom where available.
Recommended
Medical Equipment Long-Life-Cycle Boards
Medical imaging, patient monitoring, and laboratory diagnostic equipment originally designed in the 1990s often use the EP910LC44-40 as the central glue-logic device. Such equipment has regulatory-cleared design histories that cannot be arbitrarily changed, so OEM service organizations must source identical parts for board-level repairs. The 24 macrocells implement FDA-cleared logic functions that have passed IEC 60601-1 safety testing and cannot be re-engineered without costly recertification. Medical-grade contract manufacturers rely on franchised Altera distributors with full traceability documentation. Verified stock at the time of writing is limited to specialty brokers; medical OEMs should maintain minimum 3-year inventory buffers.
Recommended
Test & Measurement Instrumentation
Test and measurement instruments (oscilloscopes, logic analyzers, signal generators, power supplies) originally built in the late 1980s through 1990s frequently use the EP910LC44-40 for front-panel control logic, ADC/DAC interface glue, and trigger conditioning circuits. The 24 macrocells and 240 product terms provide ample capacity for multi-channel timing logic and trigger sequencing, while the 40 ns tPD suits sub-25 MHz sampling systems common in legacy scopes. Calibration and repair facilities for HP/Agilent/Keysight, Tektronix, and Fluke equipment stock the part for board-level repair; aftermarket supply is concentrated through franchised obsolete-part distributors. The PLCC-44 package is socket-friendly, simplifying field replacement.
Recommended
Bus Arbitration and Peripheral Control
Multi-master bus systems (VME, ISA, STD, Multibus I/II) employ the EP910LC44-40 to arbitrate bus requests, generate peripheral control strobes, and decode I/O port addresses. The 24 macrocells handle up to 8 bus masters with full priority encoding, while 12 dedicated inputs accommodate /BUSREQ, /BUSACK, /INT, and DMA handshake lines. Compared to discrete 74LS148 priority encoders and 74LS244 bus transceivers, the EPLD integrates arbitration, decoding, and control in one package, reducing board complexity. The 40 ns tPD aligns with VMEbus 8 MHz and STD-bus 8 MHz timing. Legacy VME SBCs from Motorola, Force Computers, and Radisys commonly used this exact part.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC44-40 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC44-35 | EP910LC44-30 | EP910LC44 | EP910LC-40 | EP910LC-40T |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel FPGA | Altera / Intel FPGA | Altera / Intel FPGA | Altera / Intel FPGA | Altera / Intel FPGA | Altera / Intel FPGA |
| Package | PLCC-44 | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) | PLCC-44 (same) |
| Propagation Delay (tPD) | 40 ns | 35 ns (-12.5%) | 30 ns (-25%) | 45 ns typical (+12.5%) | 40 ns (same) | 40 ns (same) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty-1) | USD 18.50 | USD 19.20 (estimated) | USD 21.50 (estimated) | USD 17.80 (estimated) | USD 17.50 (estimated) | USD 18.00 (estimated) |
Key Differentiators
- Slower but most cost-effective Classic EPLD grade (vs EP910LC44-30)
- Balanced speed for legacy 25 MHz designs (vs EP910LC44-35)
- Standardized Altera JEDEC programming flow (vs EP910DM/883B (military-grade windowed ceramic variant))
- Direct same-package drop-in for sourcing flexibility (vs EP910LC44 (standard grade, no speed suffix))
Design Notes
The EP910LC44-40 is obsolete and is no longer recommended for new designs. Engineers specifying this part for new products should evaluate modern Intel MAX II (EPM240T100C5N) or MAX V (5M80ZE64C5N) CPLDs, which are in production, supported by Quartus Prime, and offer more logic capacity at lower cost. However, MAX II/MAX V are NOT pin-compatible drop-ins - they require PCB redesign, JTAG programming, and re-validation. Reserve the EP910LC44-40 strictly for legacy board repair and long-life-cycle sustainment programs where re-design is not feasible.
The PLCC-44 package requires a polarized socket (e.g., 3M Textool or Aries 44-pin PLCC socket) for field-programmability and easy replacement in legacy designs. Pin 1 is at the chamfered corner; do not rely on socket orientation alone. For surface-mount designs, ensure the PCB land pattern follows JEDEC MO-047 with 1.27 mm pitch. Decoupling: place one 0.1 uF ceramic + one 10 uF tantalum capacitor within 5 mm of the VCC pins (40-44) with short traces to GND (10, 21). The 5 V supply should be filtered upstream with a ferrite bead if the design shares a 5 V rail with switching regulators.
The 40 ns tPD grade limits the EP910LC44-40 to clock rates of approximately 25 MHz (one gate delay per clock period). Designs with synchronous logic at higher frequencies will violate setup/hold margins and must use the EP910LC44-30 (30 ns, 33 MHz) or EP910LC44-35 (35 ns, 28 MHz) speed grades. For combinational decoding paths through the EPLD followed by an external latch/flip-flop, account for tPD plus external latch propagation in the timing budget. TTL inputs source/sink 20 uA/0.4 mA - sufficient for direct interface with HC/TTL logic, but LVCMOS 3.3 V signals require a level translator (e.g., 74LVC245) when interfacing with modern 3.3 V peripherals.
Place the EP910LC44-40 to minimize trace lengths from clock pins (38, 39) to the global clock distribution; long clock traces introduce skew that violates simultaneous switching margins. Route 24 I/O signals on inner PCB layers with ground reference for noise immunity in industrial environments. For bus-driving applications, ensure output enable (/OE) timing allows adequate bus turn-around (typically 15-20 ns minimum). Add a 100 kohm pull-up on the JTAG/programming enable pin if used in legacy LP6 programmer mode; otherwise tie to GND for normal operation.
Compliance Information
PLCC-44 plastic package is not RoHS compliant (uses lead-based solder plating) per original Altera product specification. Lead-free variants carry an 'N' suffix in the part number. Compliance status derived from package code 'LC' (Plastic Leaded Chip Carrier with lead finish) and not from explicit manufacturer declaration in the verified web data - marked 'unknown' where data is incomplete.
