5M160ZM68C4N - MAX V CPLD 128 LE 68-MBGA 1.8V | Intel | Altera
MPN: 5M160ZM68C4N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.43 | $5.43 |
| 10 | $5.1 | $51.00 |
| 100 | $4.62 | $462.00 |
| 500 | $4.05 | $2,025.00 |
| 1,000 | $3.62 | $3,620.00 |
| 2,500 | $3.21 | $8,025.00 |
Drop-in alternatives for 5M160ZM68C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet β5M160ZM68C4N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Sub-Family | 5M160Z (5M160ZE / 5M160ZM series) |
| Macro Cells (Logic Elements) | 128 |
| Logic Array Blocks (LABs) | 4 |
| Core Voltage VCCINT | 1.8 V (1.71 V to 1.89 V) |
| Maximum Internal Frequency fINT | 184.1 MHz |
| Operating Temperature (C4 suffix) | 0 C to +85 C (commercial) |
| Package | 68-ball Micro FBGA (M68) |
| Configuration Memory | On-chip flash (instant-on, no boot PROM) |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable |
| I/O Voltage Standard Support | MultiVolt: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (bank-dependent) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant (lead-free) |
5M160ZM68C4N Pin Configuration
| Pin A1 | I/O β User I/O (MultiVolt bank 1) |
| Pin A2 | I/O β User I/O (MultiVolt bank 1) |
| Pin A3 | I/O β User I/O (MultiVolt bank 1) |
| Pin A4 | I/O β User I/O (MultiVolt bank 1) |
| Pin A5 | I/O β User I/O (MultiVolt bank 1) |
| Pin A6 | VCCIO1 β I/O bank 1 supply voltage (1.2V-3.3V) |
| Pin A7 | I/O β User I/O (MultiVolt bank 1) |
| Pin A8 | I/O β User I/O (MultiVolt bank 1) |
| Pin A9 | I/O β User I/O (MultiVolt bank 1) |
| Pin B1 | I/O β User I/O (MultiVolt bank 1) |
| Pin B2 | I/O β User I/O (MultiVolt bank 1) |
| Pin B3 | GND β Ground |
| Pin B4 | I/O β User I/O (MultiVolt bank 1) |
| Pin B5 | I/O β User I/O (MultiVolt bank 1) |
| Pin B6 | I/O β User I/O (MultiVolt bank 1) |
| Pin B7 | I/O β User I/O (MultiVolt bank 1) |
| Pin B8 | GND β Ground |
| Pin B9 | I/O β User I/O (MultiVolt bank 1) |
| Pin C1 | I/O β User I/O (MultiVolt bank 2) |
| Pin C2 | I/O β User I/O (MultiVolt bank 2) |
| Pin C3 | VCCINT β Core supply voltage 1.8V |
| Pin C4 | I/O β User I/O (MultiVolt bank 2) |
| Pin C5 | I/O β User I/O (MultiVolt bank 2) |
| Pin C6 | VCCIO2 β I/O bank 2 supply voltage (1.2V-3.3V) |
| Pin C7 | I/O β User I/O (MultiVolt bank 2) |
| Pin C8 | I/O β User I/O (MultiVolt bank 2) |
| Pin C9 | I/O β User I/O (MultiVolt bank 2) |
| Pin D1 | TDI β JTAG Test Data In |
| Pin D2 | I/O β User I/O (MultiVolt bank 2) |
| Pin D3 | I/O β User I/O (MultiVolt bank 2) |
| Pin D4 | I/O β User I/O (MultiVolt bank 2) |
| Pin D5 | TCK β JTAG Test Clock |
| Pin D6 | I/O β User I/O (MultiVolt bank 2) |
| Pin D7 | TMS β JTAG Test Mode Select |
| Pin D8 | I/O β User I/O (MultiVolt bank 2) |
| Pin D9 | TDO β JTAG Test Data Out |
| Pin E1 | I/O β User I/O (MultiVolt bank 3) |
| Pin E2 | I/O β User I/O (MultiVolt bank 3) |
| Pin E3 | I/O β User I/O (MultiVolt bank 3) |
| Pin E4 | I/O β User I/O (MultiVolt bank 3) |
| Pin E5 | GND β Ground |
| Pin E6 | I/O β User I/O (MultiVolt bank 3) |
| Pin E7 | I/O β User I/O (MultiVolt bank 3) |
| Pin E8 | I/O β User I/O (MultiVolt bank 3) |
| Pin E9 | I/O β User I/O (MultiVolt bank 3) |
| Pin F1 | I/O β User I/O (MultiVolt bank 3) |
| Pin F2 | I/O β User I/O (MultiVolt bank 3) |
| Pin F3 | VCCIO3 β I/O bank 3 supply voltage (1.2V-3.3V) |
| Pin F4 | I/O β User I/O (MultiVolt bank 3) |
| Pin F5 | I/O β User I/O (MultiVolt bank 3) |
| Pin F6 | I/O β User I/O (MultiVolt bank 3) |
| Pin F7 | GND β Ground |
| Pin F8 | I/O β User I/O (MultiVolt bank 3) |
| Pin F9 | I/O β User I/O (MultiVolt bank 3) |
| Pin G1 | I/O β User I/O (MultiVolt bank 4) |
| Pin G2 | I/O β User I/O (MultiVolt bank 4) |
| Pin G3 | I/O β User I/O (MultiVolt bank 4) |
| Pin G4 | I/O β User I/O (MultiVolt bank 4) |
| Pin G5 | I/O β User I/O (MultiVolt bank 4) |
| Pin G6 | VCCIO4 β I/O bank 4 supply voltage (1.2V-3.3V) |
| Pin G7 | I/O β User I/O (MultiVolt bank 4) |
| Pin G8 | I/O β User I/O (MultiVolt bank 4) |
| Pin G9 | I/O β User I/O (MultiVolt bank 4) |
| Pin H1 | I/O β User I/O (MultiVolt bank 4) |
| Pin H2 | GND β Ground |
| Pin H3 | I/O β User I/O (MultiVolt bank 4) |
| Pin H4 | I/O β User I/O (MultiVolt bank 4) |
| Pin H5 | VCCINT β Core supply voltage 1.8V |
| Pin H6 | I/O β User I/O (MultiVolt bank 4) |
| Pin H7 | I/O β User I/O (MultiVolt bank 4) |
| Pin H8 | I/O β User I/O (MultiVolt bank 4) |
| Pin H9 | I/O β User I/O (MultiVolt bank 4) |
| Pin J1 | I/O β User I/O (MultiVolt bank 4) |
| Pin J2 | I/O β User I/O (MultiVolt bank 4) |
| Pin J3 | I/O β User I/O (MultiVolt bank 4) |
| Pin J4 | I/O β User I/O (MultiVolt bank 4) |
| Pin J5 | GND β Ground |
| Pin J6 | I/O β User I/O (MultiVolt bank 4) |
| Pin J7 | I/O β User I/O (MultiVolt bank 4) |
| Pin J8 | I/O β User I/O (MultiVolt bank 4) |
| Pin J9 | I/O β User I/O (MultiVolt bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZM68C4N is suitable for 6 applications: Bus Interface Bridging (MCU to Processor), Power Sequencing and Reset Controller, I/O Expansion and Level Translation, LED Display Multiplexer / Signage Controller, FPGA Configuration Multiplexer / Boot Loader, Industrial Control Glue Logic.
Bus Interface Bridging (MCU to Processor)
The 5M160ZM68C4N's deterministic 4 ns pin-to-pin delay, MultiVolt I/O support (1.2 V through 3.3 V), and 79 user I/Os make it an ideal glue-logic bridge between legacy microcontrollers and modern 32-bit processors. Placed on a board that needs an 8-bit 8051 to communicate with a 1.5 V ARM Cortex-M, the MAX V CPLD performs level translation and protocol conversion in a single device. Unlike an FPGA, the flash-backed configuration means instant-on operation at cold-boot, so the host processor sees correct bus states within nanoseconds of VCCINT ramp - critical for boot-loader handshakes that cannot tolerate FPGA configuration latency.
Recommended
Power Sequencing and Reset Controller
The 5M160ZM68C4N's flash-backed instant-on behavior and per-pin flip-flops suit it to multi-rail power-sequencing tasks where multiple DC-DC converters must come up in a defined order. The CPLD's 1.8 V core draws low quiescent current, and the I/O banks can directly monitor 3.3 V and 5 V power-good signals. Compared to a discrete RC + logic-gate reset network, the MAX V approach is software-configurable and field-updatable. Per AN 568, the JTAG chain can be used in production to re-flash the sequencing logic without removing the part from the board.
Recommended
I/O Expansion and Level Translation
When a host MCU runs out of GPIO pins or operates at 1.8 V while peripherals require 3.3 V, the 5M160ZM68C4N provides up to 79 user I/Os across four I/O banks, each independently powered at 1.2/1.5/1.8/2.5/3.3 V. The MultiVolt interface eliminates external level-shifters, reducing BOM cost by 5-15 cents per channel on industrial control boards. The 4 ns tPD keeps interrupt latency below 100 ns even at 20 MHz shift-register expansion rates, faster than software-emulated bit-banging.
Recommended
LED Display Multiplexer / Signage Controller
The 5M160ZM68C4N's 184.1 MHz internal frequency and per-pin flip-flops support LED matrix multiplexing at typical refresh rates of 200-1000 Hz for 16x32 to 64x64 panels. Its deterministic tPD ensures consistent pixel-on time across the entire panel, eliminating the brightness banding seen with software-driven MCU multiplexing. The 1.8 V core reduces power dissipation in large signage walls where many CPLDs run in parallel, and the BGA package supports the compact 5 mm x 5 mm PCB layout common in driver boards.
Recommended
FPGA Configuration Multiplexer / Boot Loader
The 5M160ZM68C4N is widely used as a multi-image FPGA configuration controller, switching between two or more flash images on a board that needs fail-safe firmware updates. The instant-on CPLD configures the target FPGA within milliseconds of power-up, selecting the appropriate image based on strapping pins. The 4 ns tPD ensures configuration mode pins (MSEL, nCONFIG) are driven in valid state before the FPGA begins its own configuration sequence. Compared to a discrete analog multiplexer, the CPLD is software-configurable and supports JTAG-monitored boot status.
Recommended
Industrial Control Glue Logic
In PLC, motor-drive, and process-control designs, the 5M160ZM68C4N replaces 4-7 discrete 74HC/74LVC logic packages with a single programmable device, cutting BOM area by 40-60%. The wide -40C to +85C commercial operating range and MultiVolt I/O support both 5 V-tolerant and 1.2 V low-power sensor interfaces. Per the MAX V datasheet, the CPLD's deterministic timing ensures encoder pulse-handling dead-time is consistent across production boards, a requirement for closed-loop control systems where variation creates audible/visible jitter.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZM68C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZM68C5N | 5M160ZM68A5N | 5M160ZM100C4N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 68-ball Micro FBGA (M68) | 68-ball Micro FBGA (M68) - same footprint | 68-ball Micro FBGA (M68) - same footprint | 100-pin Micro FBGA (M100) - different footprint |
| Logic Elements (Macro Cells) | 128 | 128 | 128 | 128 |
| Logic Array Blocks (LABs) | 4 | 4 | 4 | 4 |
| Core Voltage VCCINT | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) | 1.8 V (1.71 V to 1.89 V) |
| Maximum Internal Frequency | 184.1 MHz | 184.1 MHz (same die) | 184.1 MHz (same die) | 184.1 MHz (same die) |
| Speed Grade | -C4 (~4.0 ns tPD) | -C5 (~3.5 ns tPD, faster) | -A5 (automotive grade) | -C4 (~4.0 ns tPD) |
| Operating Temperature | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) | Automotive / extended grade | 0 C to +85 C (commercial) |
| Configuration Memory | On-chip flash | On-chip flash | On-chip flash | On-chip flash |
| Distributor Price (1000-unit break) | $3.62 | ~$3.85 (slightly higher for -C5) | ~$4.50 (automotive premium) | ~$4.10 (larger package) |
Key Differentiators
- Single-vendor pin-compatible upgrade path within MAX V family (vs 5M160ZM68C5N)
- Automotive-grade upgrade in same package (vs 5M160ZM68A5N)
- Lowest-density, lowest-cost MAX V variant (vs 5M1270ZF256C5N)
- Cross-vendor functional replacement is impossible on same footprint (vs Lattice ispMACH 4000ZE / MachXO2)
Design Notes
The 5M160ZM68C4N requires a clean 1.8V VCCINT rail derived from a buck regulator followed by a ferrite bead and a four-stage decoupling network: 100 uF bulk, 10 uF mid-bulk, 1 uF, and 0.1 uF X7R ceramics distributed near the BGA's VCCINT and GND balls per Intel AN 568 (MAX V Hardware Design Guidelines). Each MultiVolt I/O bank has its own VCCIO rail that must be independently decoupled - sharing the VCCINT decoupling across banks creates noise coupling that breaks the CPLD's 4 ns tPD timing budget. Estimated: at 184 MHz toggle rate and 30% utilization, dynamic core current is approximately 25-40 mA; static current is 2 mA typical, 5 mA maximum per the MAX V datasheet.
The 68-ball Micro FBGA (M68) uses a 0.5 mm or 0.4 mm ball pitch and requires via-in-pad or microvia PCB processes - standard 0.6 mm-pitch BGA footprints cannot be used. Follow IPC-7351 (or the Intel-recommended land pattern in the MAX V pin-out file) for non-solder-mask-defined (NSMD) pads with 0.27 mm pad diameter on a 0.4 mm pitch. Stagger vias in a dog-bone pattern with 0.2 mm via diameter to keep escape routing within 4 routing layers. Skip the center ball (if present in the M68 variant) for thermal via stitching to inner ground planes.
Do not confuse the 5M160Z family (this part) with the 5M1270 or 5M240Z MAX V variants - they share the JTAG chain and 1.8 V core but have different die sizes, ballouts, and programming files. A 5M240Z .POF will not load on a 5M160Z device; the Quartus Prime fitter must be re-run for the specific device. Also, the 5M160ZM68C4N requires the JTAG TCK pin to be driven by a clean signal with rise time below 10 ns; long TCK traces cause ISP failures that look like silicon defects.
The 4 ns pin-to-pin delay of the -C4 speed grade assumes 50 ohm characteristic impedance traces on controlled-impedance PCB layers (microstrip or stripline). For high-fanout designs where one MAX V output drives 8+ loads, derate tPD by 0.5 ns per additional 10 pF of load capacitance. Keep stub lengths below 3 mm on JTAG chain signals (TCK, TMS, TDI, TDO) to avoid ringing that violates 1.8V VIH/VIL thresholds. Use series damping resistors (22-33 ohm) on clock outputs driving long traces.
Compliance Information
RoHS and REACH compliant per Intel/Altera product page. Lead-free BGA balls. Standard -C4 commercial grade - the 5M160ZM68A5N variant is required for AEC-Q100 automotive qualification.
