EP20K400CFC672-9 - APEX 20K 400K Gates FPGA 672-BGA | Altera
MPN: EP20K400CFC672-9 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $485 | $485.00 |
| 10 | $446 | $4,460.00 |
| 100 | $405 | $40,500.00 |
| 500 | $365 | $182,500.00 |
| 1,000 | $325 | $325,000.00 |
EP20K400CFC672-9 Overview
An FPGA (Field Programmable Gate Array) is a programmable logic device that combines configurable logic blocks (LEs), programmable routing, and embedded memory resources onto a single die. APEX-20KC is positioned in the broader taxonomy as: FPGA > Programmable Logic Device (PLD) > Logic IC > Integrated Circuit > Semiconductor. The -KC suffix denotes an enhanced-memory variant of APEX-20K with embedded system blocks capable of dual-port RAM, content-addressable memory (CAM), and product-term logic, extending the device into datapath-intensive applications.
Key features of the EP20K400CFC672-9 include 1664 logic elements, 212,992 bits of embedded memory distributed across ESBs, True-LVDS support, multi-voltage I/O (1.5 V, 1.8 V, 2.5 V, 3.3 V) with hot-socketing capability, four phase-locked loops (PLLs) for clock management, and the FastTrack continuous interconnect architecture. The 672-ball FCBGA at 27 mm × 27 mm body provides high-density I/O suitable for high-pin-count data-path and telecom designs.
Typical applications for the EP20K400CFC672-9 include custom DSP datapaths, telecom line-card glue logic, broadband aggregation switches, PCI/PCI-X bus bridges, and custom processor peripheral controllers. The large ESB memory bank and 488 user I/Os make it well-suited for high-throughput parallel data-pump designs.
Designers should review the APEX 20KC data sheet for Quartus II device support status, configuration scheme selection (EPC configuration devices or JTAG), and proper decoupling of the 1.8 V core rail and 3.3 V auxiliary supply. Devices of this family have been classified as not recommended for new designs (NRND) and should be replaced by Cyclone, Stratix, or Arria series parts for new programs.
This page aggregates distributor stock and pricing, package-level drop-in equivalents from the Site MPN list, and design considerations that are not consolidated in any single distributor listing.
Drop-in alternatives for EP20K400CFC672-9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400CFC672-9 (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Family, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400CF672C9
✅ Drop-In✓ In Stock
$390.4 / Unit
View Datasheet →EP20K400CF672C9N
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K400CF672I9
✅ Drop-In✓ In Stock
$120 / Unit
View Datasheet →EP20K400CF672C8
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →EP20K400CF672C7
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400CF672C9ES
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP20K400CFC672-9 Maximum Ratings & Electrical Characteristics
| Family | APEX-20KC |
| Logic Elements / Macrocells | 1664 |
| Typical Gate Count | 400,000 gates |
| Embedded Memory (ESB) | 212,992 bits |
| User I/O Count | 488 |
| PLLs | 4 |
| Core Supply Voltage | 1.71 V to 1.89 V |
| I/O Supply Voltage | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature (TJ) | 0 °C to 85 °C |
| Speed Grade | -9 (commercial, slowest bin) |
| Package | 672-ball FineLine BGA (FCBGA) |
| Package Body Size | 27 mm × 27 mm |
| Mounting Type | Surface Mount (BGA) |
| Configuration Method | EPC serial device or JTAG |
EP20K400CFC672-9 27 mm × 27 mm Pin Configuration Guide
Pin configuration for EP20K400CFC672-9 (27 mm × 27 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400CFC672-9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400CFC672-9 is suitable for 6 applications: Telecom Line-Card Glue Logic, Custom DSP Datapath / FFT Co-processor, PCI / PCI-X Bus Bridge, Broadband Aggregation Switch Custom Logic, Industrial Control / Machine Vision Controller, Legacy Defense / Avionics Sustainment.
Telecom Line-Card Glue Logic
The EP20K400CFC672-9 is well-suited as glue logic on telecom line cards where 488 user I/Os are needed to interface between network processors, PHY devices, and backplane transceivers. The 1664 logic elements and 212,992 bits of ESB memory are sufficient for custom protocol-bridging state machines and rate-adaptation FIFOs. Designers typically pair it with a Vitesse or Broadcom PHY and a PowerQUICC / Layer-3 processor; the APEX-20KC's multi-voltage I/O (1.5 V to 3.3 V) simplifies level translation. The commercial 0 °C to 85 °C operating range matches telecom-central-office ambient specifications.
Recommended
Custom DSP Datapath / FFT Co-processor
The EP20K400CFC672-9's ESB multipliers and dual-port RAM make it suitable as a co-processor implementing custom FFTs, FIR filters, or correlation engines in a digital signal chain. The 212,992 bits of ESB memory can be partitioned into distributed buffers and coefficient ROM, while the four PLLs provide the multiple clock domains required for parallel datapath stages. Place the APEX-20KC between the host CPU bus and high-speed ADC/DAC data converters; its 488 I/Os easily absorb wide parallel data buses. Note that -9 is the slowest speed grade - consider -7 (EP20K400CF672C7) for DSP loops where Fmax is critical.
Recommended
PCI / PCI-X Bus Bridge
The EP20K400CFC672-9 with 488 user I/Os is commonly deployed as a PCI or PCI-X bus bridge between legacy peripheral logic and a host system. The 1664 LEs and ESB-based FIFOs can implement a full 64-bit / 66 MHz PCI-X target with scatter-gather DMA, and the 3.3 V I/O bank supports the PCI signalling directly without external transceivers. The 27 mm × 27 mm BGA exposes enough I/Os to multiplex both the primary and secondary bus plus interrupt, parity, and arbiter sidebands. Pair with a PCI hot-plug controller or upstream bridge.
Recommended
Broadband Aggregation Switch Custom Logic
Broadband aggregation switch line-cards often integrate the EP20K400CFC672-9 for custom cell-tax logic, queue management, and OAM (operations, administration, maintenance) packet inspection. The 488 I/Os allow direct connection to SPI-4.2 / SFI-4 parallel interfaces on the network processor side and to multi-PHY SERDES on the line side. APEX-20KC's ESB CAM mode is useful for fast MAC-address lookup tables, while the embedded multipliers support rate-shaping calculations. Use multiple APEX-20KC devices in parallel for higher-aggregation cards.
Recommended
Industrial Control / Machine Vision Controller
Although rated for commercial 0-85 °C operation, the EP20K400CFC672-9 is found in factory-floor machine-vision controllers and motor-control logic where 488 I/Os are needed to gather many parallel encoder and sensor inputs. The APEX-20KC's multi-voltage I/O bank simplifies interfacing to 5 V sensors via 3.3 V or 2.5 V tolerant banks. Designers migrating to industrial temperature range can substitute EP20K400CF672I9 (industrial -40 to 100 °C) on the same 672-ball BGA footprint. Pair with EPC configuration memory for fast deterministic boot.
Recommended
Legacy Defense / Avionics Sustainment
Defense and avionics programs that designed around APEX-20K silicon in the early 2000s continue to source the EP20K400CFC672-9 for sustaining engineering and re-production. Rochester Electronics holds the formal Altera end-of-life inventory for many APEX-20K family parts, providing counterfeit-mitigated supply for these regulated programs. The 672-ball FineLine BGA and industrial temperature option (EP20K400CF672I9) meet the ruggedised requirements typical of avionics box-builds. New programs should not be designed around this NRND family - migrate to Cyclone IV or Cyclone V GX instead.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400CFC672-9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400CF672C9 | EP20K400CF672C9N | EP20K400CF672I9 | EP20K400CF672C8 | EP20K400CF672C7 | EP20K400CF672C9ES |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Family / Series | APEX-20KC | APEX-20KC | APEX-20KC | APEX-20KC | APEX-20KC | APEX-20KC | APEX-20KC |
| Speed Grade | -9 (slowest commercial) | C9 (slowest commercial, equivalent to -9) | C9 (slowest commercial, equivalent to -9) | I9 (slowest industrial, equivalent to -9) | C8 (~25% faster than -9) | C7 (~35% faster than -9) | C9 ES (engineering sample, equivalent to -9) |
| Operating Temperature | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (commercial) | -40 °C to 100 °C (industrial) | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (commercial) |
| Logic Elements | 1664 | 1664 | 1664 | 1664 | 1664 | 1664 | 1664 |
| User I/Os | 488 | 488 | 488 | 488 | 488 | 488 | 488 |
Key Differentiators
- Drop-in compatibility with the EP20K400CF672C9 / C9N variants (vs EP20K400CF672C9)
- Extended industrial temperature range option (I9 variant) (vs EP20K400CF672I9)
- Faster speed-grade drops in same package (vs EP20K400CF672C7)
Design Notes
EP20K400CFC672-9 requires a 1.71 V to 1.89 V VCCINT core rail plus a separate VCCIO rail (1.5 V / 1.8 V / 2.5 V / 3.3 V per bank) and a VCCPD rail for the configuration I/O. Place at least 0.1 µF decoupling on every supply-pin pair, with bulk 22 µF tantalums or polymer caps adjacent to each supply island. Sequence VCCINT before VCCIO and ensure monotonic ramp - the APEX-20KC data sheet specifies a 0.5 ms to 100 ms ramp window. Estimated: at typical -9 commercial quiescent the device draws approximately 0.4 A from VCCINT plus I/O-bank leakage.
The 672-ball FineLine BGA at 27 mm × 27 mm demands a 4- to 6-layer PCB with dedicated power and ground planes under the device. Use 0.5 mm ball pitch with non-solder-mask-defined (NSMD) pads and microvia-in-pad if the PCB house supports it. Route all eight PLL supply pairs (VCC_PLL, GND_PLL) directly to plane islands, and provide ground cut-outs under the four PLL regions. JTAG pins TCK, TMS, TDI, TDO must be routed as a bus with 10 kΩ pull-ups on TMS and TDI; the nCONFIG and nSTATUS pins need 4.7 kΩ pull-ups to VCCIO of the configuration bank.
Estimated: at maximum toggle rate (488 I/Os at 100 MHz, 1.8 V VCCINT) the device can dissipate 1.5 W to 2.5 W, with the FineLine BGA offering a typical θJA of 8-12 °C/W with proper PCB thermal via array. For -9 commercial (0-85 °C) operation a 4×4 thermal via array under the centre die is generally sufficient; for industrial -I9 variants in enclosed enclosures add a heat spreader or forced airflow. Monitor the on-chip temperature-sense diode via JTAG for in-system thermal validation.
Do not assume the APEX-20KC is supported by current Quartus Prime releases - use Quartus II version 13.0sp1 or older for compilation. The 'C' (commercial) vs 'I' (industrial) temperature grade is encoded differently in the original -9 suffix (C9) vs the I-suffix style; verify the temperature grade before placing the order. Configuration bitstreams are not forward-compatible with later Altera families - a Quartus II APEX-20KC bitstream will not load on a Cyclone or Stratix device. Plan bitstream storage in an EPC16 (parallel) or EPCS (serial) configuration device sized for the 1.6 Mbit APEX-20KC configuration image.
Compliance Information
RoHS / REACH / lead-free status for the EP20K400CFC672-9 (the original -9 commercial speed-grade) was not present in the verified web data. The 'N'-suffix variants in the APEX-20KC family are Pb-free reflow-rated, but the base -9 ordering part number should be confirmed with the supplier (Rochester Electronics or Altera/Intel) before committing to a Pb-free assembly process. AEC-Q100 is not applicable - the APEX-20KC is a commercial/industrial FPGA, not an automotive-qualified IC.
