EP20K600CF672-2 - 600K Gates APEX 20KC FPGA | Intel / Altera
MPN: EP20K600CF672-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $917 | $917.00 |
| 10 | $880 | $8,800.00 |
| 100 | $820 | $82,000.00 |
| 500 | $750 | $375,000.00 |
| 1,000 | $680 | $680,000.00 |
EP20K600CF672-2 Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device (PLD) that engineers configure after manufacturing to implement custom digital circuits. APEX 20KC sits within the broader taxonomy of PLDs -> FPGAs -> programmable logic -> digital ICs -> semiconductors, and is built on a 0.18-micron CMOS process. The -2 speed grade places this part in the mid-tier performance bin of the APEX 20KC family, trading off some Fmax for a more attractive price compared to -3 grade variants.
Key features include 4 PLLs for clock management, a MultiCore architecture combining embedded memory (ESBs) with LUT-based logic, LVTTL/LVCMOS and other I/O standards, and JTAG-based IEEE 1149.1 boundary-scan support for in-system configuration and debug. The EPC interface enables enhanced configuration schemes including fast passive parallel and serial modes, allowing rapid field reconfiguration in production systems.
Architecture-wise, the APEX 20KC family uses a MultiCore interconnect fabric that wires LUTs, product-term logic, and embedded system blocks (ESBs) together via continuous high-performance routing. This hybrid architecture is well-suited to designs that mix wide datapath logic with on-chip FIFOs, dual-port RAM, or content-addressable memory. The 672-ball FCBGA package provides a dense, surface-mount interconnect suitable for high-speed signals.
Typical applications include telecom line cards, high-speed serial backplanes, industrial motor control, and DSP co-processing. The part's combination of logic density, on-chip memory, and PLL resources makes it particularly attractive for multi-channel basestation and signal-conditioning subsystems where integration reduces board complexity.
When designing with this device, ensure your Quartus II (or legacy MAX+PLUS II) toolchain supports the APEX 20KC device family, and verify that the -2 speed grade meets your critical-path timing closure. Power sequencing of VCCINT and VCCIO rails must follow Intel's recommended ramp order to avoid in-rush latch-up.
Drop-in alternatives for EP20K600CF672-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672-2 (same form factor and footprint) — differing in Process Technology, Package, Operating Temperature, Speed Grade, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672-1X
✅ Drop-In✓ In Stock
$95 / Unit
View Datasheet →EP20K600CF672
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Contact for price
View Datasheet →EP20K400CF672C-7
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$171 / Unit
View Datasheet →EP20K400CF672C7
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$195 / Unit
View Datasheet →EP20K400CF672C8
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$108 / Unit
View Datasheet →EP20K600CF672-2 Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel / Altera |
| Series | APEX 20KC |
| Device Family | APEX 20KC PLD |
| Gate Count (typical) | 600,000 gates |
| Logic Elements | 30,720 |
| Embedded RAM (approx.) | 311,232 bits |
| Process Technology | 0.18 um CMOS |
| Speed Grade | -2 |
| Package Type | 672-ball FineLine BGA (FCBGA) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +60 C (TJ, per Alibaba supplier listing) |
| Configuration Mode | Enhanced Configuration (EPC) |
| Number of PLLs | 4 |
| I/O Standards | LVTTL, LVCMOS, and others per datasheet |
| Boundary Scan | IEEE 1149.1 (JTAG) |
| Lifecycle Status | Obsolete / last-time-buy |
EP20K600CF672-2 Pin Configuration
| Pin A1 | I/O — General-purpose user I/O bank |
| Pin A2 | I/O — General-purpose user I/O bank |
| Pin A3 | I/O — General-purpose user I/O bank |
| Pin B1 | I/O — General-purpose user I/O bank |
| Pin B2 | VCCIO — I/O supply voltage |
| Pin B3 | GND — Ground reference |
| Pin C1 | I/O — General-purpose user I/O bank |
| Pin C2 | I/O — General-purpose user I/O bank |
| Pin C3 | TMS — JTAG test mode select |
| Pin D1 | TCK — JTAG test clock |
| Pin D2 | TDO — JTAG test data out |
| Pin D3 | TDI — JTAG test data in |
| Pin E1 | nSTATUS — Configuration status |
| Pin E2 | nCONFIG — Configuration control |
| Pin E3 | DCLK — Configuration clock |
| Pin F1 | DATA0 — Configuration data |
| Pin F2 | VCCINT — Core supply voltage |
| Pin F3 | GND — Ground reference |
| Pin G1 | I/O — General-purpose user I/O bank |
| Pin G2 | I/O — General-purpose user I/O bank |
| Pin G3 | I/O — General-purpose user I/O bank |
Typical Applications
EP20K600CF672-2 is suitable for 7 applications: Telecom Line-Card Interface, High-Speed Serial Backplane Bridging, Industrial Motor Control, DSP Co-Processing / FIR Filter Banks, Legacy ASIC Prototyping, Test & Measurement Instrumentation Front-End, Network Router / Switch Aggregation.
Telecom Line-Card Interface
The EP20K600CF672-2 is well-suited to telecom line-card designs where 600K gates of LUT and product-term logic implement protocol engines (UTOPIA, POS-PHY, SPI), framing, and link-layer state machines. Its 4 on-chip PLLs cleanly derive multiple clock domains from a single backplane reference, while the 311 Kbits of embedded RAM provides per-channel FIFOs without external SRAM. The FCBGA-672 package keeps high-speed bus traces short, meeting the signal-integrity demands of 155-622 Mbps interfaces typical in legacy SONET/SDH and ATM equipment.
Recommended
High-Speed Serial Backplane Bridging
In backplane bridging applications, the APEX 20KC's MultiCore fabric wires parallel datapath logic to embedded SERDES-like I/O via LVDS-compatible pins, aggregating lower-speed links into wider buses. The EP20K600CF672-2's 488 user I/Os and 4 PLLs enable multi-channel aggregation across 8-16 parallel lanes with independent clock synthesis. Its commercial temperature range suits central-office environments, and the 672-ball FCBGA's ground-pad structure aids EMI control on dense line cards.
Recommended
Industrial Motor Control
Industrial servo and inverter controllers benefit from the EP20K600CF672-2's mix of wide datapath arithmetic (PWM generation, vector rotation) and product-term glue logic (fault handling, dead-time insertion). The 4 PLLs derive high-resolution PWM carrier clocks from a low-frequency reference, and the 311 Kbits of RAM hold look-up tables for sinusoidal and space-vector modulation. The commercial 0-60 C junction range suits enclosed control cabinets; for harsh environments, migrate to the APEX 20KC industrial -I suffix variants.
Recommended
DSP Co-Processing / FIR Filter Banks
The APEX 20KC's LUT fabric implements fast-parallel FIR and IIR filters at sample rates exceeding 100 MHz when used in distributed-arithmetic mode. The EP20K600CF672-2 supports 8-16 channel filter banks with coefficients stored in embedded RAM, updated dynamically from a host processor. The 4 PLLs align sampling clocks to system frame sync, and the EPC interface permits in-field coefficient updates via JTAG. This architecture historically displaced discrete DSP chips in cost-sensitive multi-channel audio and vibration-analysis designs.
Recommended
Legacy ASIC Prototyping
The EP20K600CF672-2 is commonly used as a prototype vehicle for ASICs in the 200K-500K-gate range, offering early silicon-validated logic before tape-out. The MultiCore architecture's mix of LUT and product-term logic mirrors ASIC gate-array structures, easing migration. JTAG boundary scan and EPC configuration allow rapid iteration, and the FCBGA-672 package replicates the ball pitch of many ASIC packages, simplifying footprint-accurate prototype boards. Engineers port the verified RTL to a target ASIC foundry once design is stable.
Recommended
Test & Measurement Instrumentation Front-End
Test instruments such as logic analysers, protocol exercisers, and ATE pin-electronics cards leverage the EP20K600CF672-2's 488 I/Os and LUT-rich fabric to implement pattern generators, comparators, and timing generators. The 4 PLLs derive multiple precisely-skewed clocks for source-synchronous interfaces, while 311 Kbits of embedded RAM buffer captured waveforms. The 672-ball FCBGA delivers the high pin density needed for 32-64 channel cards, and Quartus II's gate-level timing closure tools simplify timing-margin analysis on critical paths.
Recommended
Network Router / Switch Aggregation
Mid-generation routers and Layer-2/3 switches use the EP20K600CF672-2 in FCBGA-672 to implement packet-classification engines, queue managers, and protocol-terminating interfaces. Its 600K gates handle multi-gigabit lookups while 311 Kbits of dual-port RAM act as on-chip cell/packet buffers, off-loading the external TCAM and SRAM. The 4 PLLs synthesise independent clocks for fabric, PHY, and CPU interfaces, and the EPC configuration supports secure field upgrades. Commercial temp range fits climate-controlled telecom closets.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672-1X | EP20K600CF672 | EP20K400CF672C-7 | EP20K400CF672C7 | EP20K400CF672C8 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FCBGA | 672-ball FCBGA - same | 672-ball FCBGA - same | 672-ball FCBGA - same | 672-ball FCBGA - same | 672-ball FCBGA - same |
| Gate Count | 600,000 | 600,000 | 600,000 | 400,000 (-33%) | 400,000 (-33%) | 400,000 (-33%) |
| Speed Grade | -2 | -1X (faster) | unspecified | -7 | -7 | -8 |
| Embedded RAM | 311,232 bits | 311,232 bits | 311,232 bits | 212,992 bits (-32%) | 212,992 bits (-32%) | 212,992 bits (-32%) |
| Logic Elements | 30,720 | 30,720 | 30,720 | 16,640 (-46%) | 16,640 (-46%) | 16,640 (-46%) |
| Number of PLLs | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature | 0 C to +60 C (commercial) | 0 C to +60 C (commercial) | 0 C to +60 C (commercial) | 0 C to +60 C (commercial) | 0 C to +60 C (commercial) | 0 C to +60 C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest-density APEX 20KC option with on-die PLLs (vs EP20K400CF672C-7)
- Mid-tier speed grade balances cost and Fmax (vs EP20K600CF672-1X)
- 672-ball FCBGA offers highest I/O count in the family (vs EP20K600CB652C7)
- On-chip PLL resources eliminate external clock-gen chips (vs Discrete CPLD + PLL design)
Design Notes
Estimated: Quartus II dropped APEX 20KC device support after v9.1, so engineers maintaining legacy designs must retain an older Quartus installation or migrate RTL to a current FPGA family. Newer Quartus versions will not program or bitstream-generate the EP20K600CF672-2. Confirm toolchain compatibility before committing to a long-term production build on this obsolete part.
The APEX 20KC requires carefully-sequenced VCCINT and VCCIO ramp profiles. VCCINT (core) must reach its nominal value before VCCIO reaches its nominal value to avoid in-rush current through the I/O structures that can trigger latch-up. Use a multi-rail power supervisor with programmable slew-rate tracking rather than simple RC ramps.
The 672-ball FCBGA requires a multi-layer PCB with matched-impedance routing for high-speed I/O, and a continuous ground/power plane beneath the package for thermal dissipation and return-path integrity. Use 1-oz copper outer layers plus 2-oz inner planes, and follow Altera's recommended footprint with non-solder-mask-defined (NSMD) pads for reliable BGA joint formation.
Place decoupling capacitors on every VCCINT and VCCIO ball pair, ideally 0.1 uF X7R ceramics in 0402 or 0201 size, with bulk 10-100 uF tantalum or polymer capacitors distributed around the BGA. The 4 PLLs each require a dedicated analog supply pin pair and an LC pi-filter for low-jitter clock multiplication - sharing these pins with digital supplies will degrade jitter performance.
Source-synchronous interfaces (LVDS, DDR-style buses) on the EP20K600CF672-2 require matched-length traces within ±25 mil for the clock and data pair, with intra-pair skew of 50 mil or less. Use series-termination resistors placed near the driver pin, and avoid via stubs on high-speed nets. Simulate critical buses with IBIS models provided by Altera in the device literature.
Compliance Information
APEX 20KC is an obsolete Altera/Intel FPGA family manufactured on a 0.18 um process prior to current RoHS / REACH compliance documentation standards. Compliance status not explicitly published in the Verified Web Data; marked unknown. Not AEC-Q100 qualified (commercial-temperature part).
