EP20K400CF672C9ES - 400K Gate APEX 20KC FPGA 672-FCBGA | Altera
MPN: EP20K400CF672C9ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $230 | $23,000.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $168 | $168,000.00 |
EP20K400CF672C9ES Overview
An APEX 20KC FPGA is a member of Altera's APEX (Advanced Programmable Element Matrix) family of high-density programmable logic devices, positioned in the broader hierarchy of programmable logic (PLD -> CPLD/FPGA -> APEX family -> high-density SRAM-based FPGA -> semiconductor). The 'C' suffix denotes the commercial temperature grade (0 °C to +85 °C), and the 9 speed grade indicates the slowest of three tiers in the APEX 20KC family, trading timing margin for lower unit cost in non-timing-critical designs.
Key features include 16,640 logic elements, 488 kbit of embedded system memory (ESB) configurable as RAM, ROM, or CAM, MultiVolt I/O supporting 1.8 V, 2.5 V, and 3.3 V interfaces, and a high-bandwidth True-LVDS interface. The 'ES' suffix indicates this specific part variant as ordered by Altera's ordering code system, with the device offering in-system programmability via JTAG and supporting configuration via serial or parallel PROM.
Typical applications include high-speed digital signal processing (DSP) pipelines, telecommunications backplane interfaces, PCI/PCI-X bridging, and ASIC prototyping. The 672-pin FCBGA package provides ample I/O for memory-intensive designs and multi-bank clock distribution.
When designing with this device, ensure signal integrity on the FCBGA fan-out by using microvia or via-in-pad PCB technology. Power sequencing between the 1.8 V VCCINT and VCCIO banks must follow Altera's APEX 20KC datasheet guidelines to prevent inrush current and latch-up. Decoupling requires low-ESL ceramic capacitors placed directly under the package's power/ground balls.
Drop-in alternatives for EP20K400CF672C9ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400CF672C9ES (same form factor and footprint) — differing in Operating Temperature, Package, Process Technology, Speed Grade, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400CF672C9
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View Datasheet →EP20K400CF672C8ES
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View Datasheet →EP20K400CF672C8
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View Datasheet →EP20K400CF672C8N
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View Datasheet →EP20K400CF672C8AA
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View Datasheet →EP20K400CF672C7ES
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View Datasheet →EP20K400CF672C7
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$195 / Unit
View Datasheet →EP20K400CF672C9ES Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Series | APEX-20KC |
| Logic Elements / Cells | 16640 |
| Gate Count | 400000 |
| Number of Gates | 400 K |
| Voltage - Supply (Core) | 1.8 V |
| Maximum Internal Frequency | 250 MHz |
| Total RAM Bits | 488 kbit |
| Process Technology | 0.18 µm CMOS |
| Number of I/O | 488 |
| Package / Case | 672-BBGA, FCBGA |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Speed Grade | 9 |
| MultiVolt I/O Support | 1.8 V / 2.5 V / 3.3 V |
| In-System Programmability | Yes (JTAG) |
| RoHS Status | Unknown |
| Lead-Free | Unknown |
EP20K400CF672C9ES Pin Configuration
| Pin 1 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 2 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 3 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 4 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 5 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 6 | VCCIO1 — I/O bank 1 supply (1.8/2.5/3.3 V) |
| Pin 7 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 8 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 9 | I/O Bank 1A — User I/O (bank 1A) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 12 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 13 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 14 | VCCIO1 — I/O bank 1 supply (1.8/2.5/3.3 V) |
| Pin 15 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 16 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 17 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 18 | GND — Ground |
| Pin 19 | I/O Bank 1B — User I/O (bank 1B) |
| Pin 20 | I/O Bank 1B — User I/O (bank 1B) |
Typical Applications
EP20K400CF672C9ES is suitable for 6 applications: ASIC Prototyping and Verification, Telecommunications Backplane Bridging, Digital Signal Processing Pipelines, PCI/PCI-X Bus Interface Bridges, Industrial Control and Machine Vision, Legacy Military and Aerospace Avionics.
ASIC Prototyping and Verification
The EP20K400CF672C9ES's 400,000-gate capacity and 488 user I/O make it a strong candidate for prototyping ASICs before committing to mask production. The 672-FCBGA package exposes enough pins to map ASIC boundary-scan and I/O pads 1:1. With 16,640 logic elements and 488 kbit of embedded memory, designers can verify register-transfer-level logic and on-chip bus structures. Quartus II synthesis maps the ASIC netlist directly, and the JTAG-based in-system programmability allows rapid design iteration. For ASICs targeting gate counts up to 400 K, the EP20K400CF672C9ES delivers sufficient capacity while preserving timing closure through the APEX 20KC architecture's predictable interconnect. Note that speed grade 9 limits prototype timing margins; engineers building timing-critical ASICs should choose speed grade 7 or 8 alternatives.
Recommended
Telecommunications Backplane Bridging
Telecommunications backplanes with multiple line cards require bridging FPGAs to convert between proprietary bus protocols and standard interfaces such as SPI-4.2, UTOPIA, or POS-PHY. The EP20K400CF672C9ES's 488 I/O pins comfortably accommodate parallel data buses, control signals, and clock distribution. Its True-LVDS capability supports backplane signaling at hundreds of megabits per second. The MultiVolt I/O feature (1.8 V/2.5 V/3.3 V) lets the FPGA interface with legacy 3.3 V PHY chips and modern 1.8 V ASICs on the same board. The 488 kbit embedded system memory supports cell buffering and FIFO structures needed for ATM/Packet processing. For telecom line cards designed in the early 2000s, the EP20K400CF672C9ES remains a supported legacy component.
Recommended
Digital Signal Processing Pipelines
DSP pipelines for audio, video, and baseband processing benefit from the EP20K400CF672C9ES's 16,640 logic elements, which can implement parallel multiply-accumulate (MAC) units, FIR filters, and FFT butterfly structures. The 488 kbit of embedded system memory serves as coefficient ROM and sample buffers, avoiding external SRAM access latency. At speed grade 9, the part supports FFT sizes up to 1024 points at moderate sample rates. The 672-FCBGA package's 488 I/O allow wide data buses to external SDRAM and DAC/ADC chips. For wireless base stations and software-defined radio prototypes, this part provides sufficient gate count for multi-channel DSP while fitting the APEX 20KC's 0.18 µm process power envelope.
Recommended
PCI/PCI-X Bus Interface Bridges
The EP20K400CF672C9ES is well-suited for PCI and PCI-X bridge applications where a 32-bit or 64-bit PCI bus must be translated to a local processor or memory bus. Its 488 I/O provide enough pins to support the full PCI-X 64-bit/133 MHz bus (94 pins) plus local bus, memory interface, and JTAG. The 400,000-gate capacity easily fits a PCI-X target controller, DMA engine, and address-translation logic. MultiVolt I/O supports the 3.3 V signaling required by PCI and 5 V tolerance through external bus switches. Industrial PCs, embedded servers, and legacy add-in cards rely on the EP20K400CF672C9ES for this bridging role, and the part's longevity in production systems makes it a stable choice for long-life-cycle products.
Recommended
Industrial Control and Machine Vision
Industrial control systems and machine-vision cameras require FPGAs to aggregate data from multiple sensors, perform real-time image preprocessing, and drive high-speed interfaces to host PCs. The EP20K400CF672C9ES's 488 I/O can interface with parallel CMOS image sensors, encoders, and Camera Link transmitters. Its 16,640 logic elements implement Bayer-to-RGB conversion, edge detection, and histogram equalization pipelines. The commercial 0-85 °C temperature range is adequate for factory-floor enclosures with active cooling. Industrial designs that have been in production for 15+ years continue to use the EP20K400CF672C9ES because its silicon revision is stable and the bitstream is fully verified.
Recommended
Legacy Military and Aerospace Avionics
Although the EP20K400CF672C9ES is a commercial-grade part, long-life defense and aerospace programs have integrated it into legacy avionics where re-certification costs make redesign prohibitive. The 672-FCBGA package's thermal characteristics and the part's stable silicon revision (no die shrinks) suit programs with multi-decade support requirements. With 16,640 logic elements, the part handles MIL-STD-1553 bus interfaces, ARINC 429 channels, and discrete I/O expansion for flight-control computers. For new designs, the EP20K400CF672C9ES is not recommended because obsolete parts face supply risks; however, for sustaining engineering of fielded systems, it remains a viable option sourced from authorized obsolete-stock distributors.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400CF672C9ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400CF672C9 | EP20K400CF672C8ES | EP20K400CF672C8 | EP20K400CF672C8N | EP20K400CF672C8AA | EP20K400CF672C7ES | EP20K400CF672C7 |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-BBGA, FCBGA | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same | 672-BBGA, FCBGA - same |
| Speed Grade | 9 | 9 | 8 (faster) | 8 (faster) | 8 (faster, lead-free) | 8 (faster, AA suffix) | 7 (fastest) | 7 (fastest) |
| Gate Count | 400 K | 400 K | 400 K | 400 K | 400 K | 400 K | 400 K | 400 K |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Embedded Memory | 488 kbit | 488 kbit | 488 kbit | 488 kbit | 488 kbit | 488 kbit | 488 kbit | 488 kbit |
| Maximum Frequency | 250 MHz | 250 MHz | >250 MHz (faster grade) | >250 MHz (faster grade) | >250 MHz (faster grade) | >250 MHz (faster grade) | >250 MHz (fastest grade) | >250 MHz (fastest grade) |
| Number of I/O | 488 | 488 | 488 | 488 | 488 | 488 | 488 | 488 |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C |
Key Differentiators
- Identical silicon to the EP20K400CF672C9 base part, distinguished only by ordering-code suffix (vs EP20K400CF672C9)
- Speed grade 9 trades timing margin for lower unit cost in non-critical designs (vs EP20K400CF672C8ES)
- Lower-density FPGA option available in same 672-FCBGA family for cost-down flexibility (vs EP20K300EFC672-2X)
Design Notes
The 672-FCBGA package has a 1.0 mm ball pitch, requiring high-density PCB fabrication with microvia (laser-drilled) stack-up to escape signals from inner balls. Standard 4-layer FR-4 boards cannot reliably route this package; use 6+ layer boards with sequential lamination. Place at least 8 decoupling capacitors (0.1 µF X7R) directly under the package power/ground balls and 4 bulk capacitors (10 µF tantalum or ceramic) within 1 cm of the VCCINT balls. Maintain a continuous ground plane beneath the package and avoid signal routing on layers directly under the BGA to preserve power integrity.
VCCINT (1.8 V core) must be sequenced before or simultaneously with VCCIO (1.8/2.5/3.3 V bank supplies). Per Altera APEX 20KC datasheet guidelines, inrush current during power-up can exceed 5 A if sequencing is violated, triggering latch-up. Use a power-management IC with controlled rise time (1-10 ms) or a discrete RC delay circuit. The 1.8 V regulator must source at least 1.5 A continuous (typical core current at 250 MHz is ~700 mA, plus margin). Add a 100 µF bulk capacitor at the regulator output and a ferrite bead in series with VCCIO if multiple banks run at different voltages.
Common mistakes when designing with the EP20K400CF672C9ES include: (1) using speed grade 9 in timing-critical paths where speed grade 7 or 8 is required - the 9 grade has the slowest internal timing and will fail timing closure for designs targeting >180 MHz; (2) omitting the JTAG chain termination - this prevents in-system programming; (3) confusing 'ES' with 'engineering sample' - in Altera's ordering system, 'ES' is a suffix code, not an ES grade. When substituting, always verify the exact ordering code against Altera's legacy part-numbering guide. For production, source from authorized distributors to avoid counterfeit risk, especially given the part's obsolete status.
Compliance Information
RoHS, REACH, lead-free, and halogen-free compliance not specified in verified distributor data. The APEX 20KC family predates mainstream RoHS adoption (2006); contact distributors for batch-specific compliance certificates. Not AEC-Q100 qualified (commercial-grade part).