EP20K400FI672-1N - APEX 20K 400K Gates FPGA, 672-BGA | Intel / Altera
MPN: EP20K400FI672-1N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP20K400FI672-1N Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device (PLD) that combines the integration density of an ASIC with the design flexibility of in-system reconfigurability. Within the broader semiconductor taxonomy, an FPGA sits under programmable logic ICs -> logic ICs -> integrated circuits. APEX 20K belongs to the second-generation multi-core architecture family, which preceded the Stratix / Cyclone lines and remains supported through Altera's legacy device programs for long-life-cycle industrial, telecom, and defense designs.
Key features include 16,640 logic elements, 212,992 RAM bits distributed across ESBs, 4 phase-locked loops (PLLs), 502 user I/O pins, support for multiple I/O standards (LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, HSTL, LVDS), and in-system programmability via IEEE 1149.1 JTAG or passive serial configuration. The device operates from a 2.5V core supply with separate VCCIO banks for I/O standard compatibility.
Architecturally, the EP20K400 combines 16 MegaLAB structures, each containing 16 LABs and one ESB, providing a regular fabric that simplifies timing closure and floorplanning. The 672-ball FineLine BGA offers high signal density for designs requiring hundreds of I/O, while the 26x26 mm body suits high-density PCB layouts. The "-1" speed grade provides the fastest tpd in the family, important for high-throughput datapath designs.
Typical applications include telecom infrastructure (SONET/SDH framer, ATM switch), industrial control (motion control, motor drive signal processing), test and measurement (logic analyzer capture, pattern generation), military/aerospace (radar signal preprocessing, secure communications), and legacy ASIC prototyping. The APEX 20K is widely used in long-lifecycle programs where the -40C to +85C industrial temperature range and proven process maturity outweigh the advantages of newer families.
When designing with the EP20K400FI672-1N, plan power decoupling on every VCC and VCCIO pin and provide a minimum 4-layer PCB stack-up for signal integrity on the FastTrack routing. Configuration must be driven from a compatible PROM (EPC2 or EPC16) or a microprocessor, and unused I/O banks must still be powered.
This page synthesizes distributor pricing, drop-in alternatives from the same APEX 20K family, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP20K400FI672-1N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-1N (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Speed Grade, Propagation Delay.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FI672-1
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP20K400FI672-2N
✅ Drop-In✓ In Stock
$188.75 / Unit
View Datasheet →EP20K400EFC672-3
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP20K400EFC672-2N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-1N
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K400FI672-1N Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Device | EP20K400 |
| Maximum System Gates | 1,052,032 |
| Typical Gates | 400,000 |
| Logic Elements | 16,640 |
| Embedded System Blocks (ESBs) | 104 |
| Maximum RAM Bits | 212,992 |
| PLLs | 4 |
| User I/O Pins | 502 |
| Total Terminals | 672 |
| Package | FineLine BGA-672 (26x26 mm) |
| Speed Grade | -1 (fastest) |
| Core Voltage | 2.5 V (2.375 V to 2.625 V) |
| Operating Temperature | -40C to +85C (industrial) |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| Peak Reflow Temperature | 220 C |
| RoHS Status | Compliant (Pb-free, N suffix) |
EP20K400FI672-1N fineline bga-672 (26x26 mm) Pin Configuration Guide
Pin configuration for EP20K400FI672-1N (fineline bga-672 (26x26 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-1N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-1N is suitable for 6 applications: Telecom Infrastructure (SONET/SDH Framing), Industrial Motion Control / Servo Drive, Test & Measurement Instrumentation, Military/Aerospace Signal Preprocessing, Legacy ASIC Prototyping, Network Switching Backplane.
Telecom Infrastructure (SONET/SDH Framing)
The EP20K400FI672-1N fits telecom framing applications because of its 502 user I/Os that can directly interface parallel bus framers, mappers, and pointer processors without external muxing. The 16,640 logic elements and 212,992 embedded RAM bits are sufficient to implement STS-1/STM-1 path overhead processing plus a soft processor for OA&M. Per the APEX 20K datasheet, the -1 speed grade provides sub-7 ns tpd on FastTrack routing, comfortably meeting the 51.84 MHz STS-1 clock with margin. PLLs (4) generate independent clocks for line, payload, and overhead interfaces. Industrial temperature grade (-40C to +85C) makes the part suitable for outdoor-mounted cross-connect shelves.
Recommended
Industrial Motion Control / Servo Drive
The EP20K400FI672-1N suits multi-axis servo drives by integrating encoder interfaces, PWM generation, and current/voltage PI loops in a single fabric. The 502 I/Os handle parallel encoder SSI/BiSS or EnDat channels plus resolver excitation DACs and ADC sample strobes across 4-6 axes. With -1 speed grade, the design can compute field-oriented-control (FOC) loops at 16 kHz PWM with sub-microsecond loop latency. The industrial -40C to +85C rating covers drive cabinet ambient, while the 212,992 RAM bits implement lookup tables and reference trajectory buffers. Embedded dual-port RAM blocks support simultaneous sample capture and host-side telemetry readout.
Recommended
Test & Measurement Instrumentation
The EP20K400FI672-1N is well suited for logic analyzer capture and pattern generator cards where its 502 I/Os can directly sample or drive bus widths up to 64 bits per channel plus protocol-aware state machines. The 16,640 logic elements implement data compression, run-length encoding, and trigger sequencers that fit between 200 MHz and 400 MHz internal clock rates available from the 4 PLLs. Per the APEX 20K datasheet, the -1 speed grade is required to meet 200 MHz timing closure for high-speed capture. 672-ball FineLine BGA enables dense probe-card layouts, and the industrial temperature grade allows bench and field-deployed instruments.
Recommended
Military/Aerospace Signal Preprocessing
The EP20K400FI672-1N is widely deployed in defense radar, electronic warfare, and secure communications where long lifecycle, radiation-tolerant packages, and Altera legacy support are valued. The 502 I/Os interface ADC/DAC arrays, while 16,640 logic elements implement digital down-conversion (DDC), pulse compression, and beamforming preprocessing. Industrial temperature rating and Pb-free assembly suit defense electronics manufacturing. Per Intel's legacy device program, APEX 20K remains available for long-life aerospace programs. The 672-ball FineLine BGA enables compact line-replaceable module (LRM) layouts.
Recommended
Legacy ASIC Prototyping
The EP20K400FI672-1N functions as an ASIC prototyping vehicle for designs that target 400K-gate ASICs because the APEX 20K fabric maps cleanly from Verilog/VHDL synthesis with predictable timing closure on FastTrack interconnect. The 502 I/Os replicate ASIC pad ring requirements, while 16,640 logic elements are partitioned to mirror the ASIC block hierarchy. Designers can use 212,992 RAM bits to model ASIC SRAM macros, and the 4 PLLs generate ASIC clock trees. The -1 speed grade allows prototyping at ASIC target clock speeds up to ~150 MHz, and the same Quartus II design flow supports both APEX 20K and ASIC handoff.
Recommended
Network Switching Backplane
The EP20K400FI672-1N is well-matched to multi-Gigabit Ethernet switch line cards requiring dozens of SGMII / LVDS lanes and centralized queuing logic. Its 502 I/Os support multiple PHY-2 interfaces and fabric-side SERDES links via LVDS, while 16,640 logic elements implement shared-memory queue managers and packet classifiers. Per the APEX 20K datasheet, the part supports 3.3V PCI I/O directly, simplifying legacy line-card designs. Industrial temperature grade suits carrier-grade equipment, and lead-free N suffix assembly meets modern telecom OEM compliance.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-1N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FI672-1 | EP20K400FI672-2N | EP20K400EFC672-3 | EP20K400EFC672-2N | EP20K400EFC672-1N |
|---|---|---|---|---|---|---|
| Package | FineLine BGA-672 | FineLine BGA-672 - same | FineLine BGA-672 - same | FineLine BGA-672 - same | FineLine BGA-672 - same | FineLine BGA-672 - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | -1 (fastest) | -1 (fastest) | -2 (slower) | -3 (slowest) | -2 (slower) | -1 (fastest) |
| Core Voltage | 2.5 V (F-suffix) | 2.5 V (F-suffix) | 2.5 V (F-suffix) | 1.8 V (E-suffix) | 1.8 V (E-suffix) | 1.8 V (E-suffix) |
| Lead-Free (N suffix) | Yes | No (non-N) | Yes | No (non-N) | Yes | Yes |
| User I/O Pins | 502 | 502 | 502 | 502 | 502 | 502 |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 |
| Embedded RAM Bits | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest-speed industrial-grade APEX 20K variant in 672-ball BGA (vs EP20K400FI672-2N)
- Lead-free RoHS-compliant assembly (N suffix) (vs EP20K400FI672-1)
- Standard 2.5V core for compatibility with legacy designs (vs EP20K400EFC672-1N)
Design Notes
The EP20K400FI672-1N core draws approximately 0.5-1.5 A depending on utilization and clock rate, supplied at 2.5V on VCCINT pins. Each of the 502 I/O pins draws up to 25 mA DC; bank VCCIO supplies should be sized for worst-case simultaneous switching using the IBIS model. Per the APEX 20K datasheet, all VCC and VCCIO pins must be connected to a low-impedance plane with at least one 0.1 uF decoupling capacitor per power pin; bulk 100 uF tantalum or polymer caps at each regulator are recommended. PLL analog VCC pins (VCC_PLL) require dedicated ferrite-isolated 2.5V supplies with pi-filter (10 uF + bead + 10 uF) to meet jitter specifications.
A minimum 4-layer PCB stack-up with continuous ground and power planes is required for the 672-ball FineLine BGA. The 1.27 mm ball pitch demands 0.2 mm vias-in-pad with filled and plated-over copper for escape routing; signal layers should use 0.1 mm traces on 0.2 mm pitch. Per the APEX 20K handbook, microstrip-controlled impedance of 50 ohm single-ended or 100 ohm differential must be verified for all high-speed LVDS/GTL+ signals. BGA underfill or corner staking is recommended for vibration-prone environments.
Do not leave any VCC or VCCIO pin floating - even unused I/O banks must be powered to prevent I/O buffer back-powering through ESD diodes. nCONFIG must be held low during power ramp until all rails stabilize, then released to start configuration. Per the APEX 20K datasheet, JTAG chain TMS and TCK require 10 kohm pull-ups; DATA0 in passive serial mode must be driven from the configuration device. Check that all JTAG pins share a common reference plane to avoid false TDO data at power-up.
Compliance Information
RoHS compliant per N suffix in MPN and Pb-free BGA balls. AEC-Q100 not applicable - APEX 20K is not automotive qualified. Halogen-free status not explicitly stated in datasheet; refer to Intel/Alt
