EP20K400FI672-1 - 400K APEX-20K FPGA 672-BGA | Altera / Intel
MPN: EP20K400FI672-1 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118 | $11,800.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92 | $92,000.00 |
EP20K400FI672-1 Overview
What is an FPGA? An FPGA (Field-Programmable Gate Array) is a reconfigurable digital integrated circuit whose logic fabric, interconnect, and I/O cells can be programmed by the end user after manufacture, sitting in the taxonomy: programmable logic device → CPLD/FPGA → semiconductor → integrated circuit. The APEX 20K family pioneered Altera's multi-level look-up table plus embedded memory architecture, combining fine-grained logic with system-level blocks (ESBs) for memory and arithmetic, and is hierarchically positioned as: APEX 20K → APEX family → Altera high-density FPGA → programmable logic device family.
Key features of the EP20K400FI672-1 include 212,992 logic elements, 16,640 LABs (Logic Array Blocks), 502 user I/O lines, 4 dedicated inputs, an internal CMOS core, a -1 speed grade, and industrial operating temperature. The 'F' suffix denotes a FineLine BGA package, the 'I' denotes industrial temperature, and '672' denotes the 672-pin BGA ball grid. The device integrates ESBs (Embedded System Blocks) that provide on-chip dual-port RAM and CAM with widths up to 32 bits.
Typical applications include telecommunications infrastructure (ATM switch fabrics, SONET/SDH framing, DSLAMs), high-speed data-path prototyping, DSP co-processing, glue-logic integration in ASIC prototyping, and PCI/PCI-X bus bridges where the 502 I/O are sufficient to terminate 64-bit buses with parity. The architecture's parallel multiplier support and on-chip memory make it suitable for pre-processing pipelines feeding external processors.
When designing with the EP20K400FI672-1, engineers must observe Altera's APEX 20K I/O assignment guidelines, use the Quartus II design tool (which supports legacy APEX devices via the MAX+PLUS II or Quartus MAX device support path), and respect the LVCMOS/LVTTL I/O standard supply sequencing. Because the part is mature and on Altera/Intel last-time-buy or obsolete status, sourcing should be qualified against authorized distributors and qualified aftermarket channels.
This page synthesizes distributor stock indicators, same-family drop-in pin-compatible variants, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP20K400FI672-1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-1 (same form factor and footprint) — differing in Operating Temperature, Package, Series, Family, Logic Elements.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFI672-2X
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP20K400EFI672-2N
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EP20K400EFC672-1
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400EFC672-3
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP20K400EBC652-1
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400FI672-1 Maximum Ratings & Electrical Characteristics
| Series | APEX 20K |
| Device Family | APEX-20K Field Programmable Gate Array |
| Typical Gates | 400,000 |
| Logic Elements | 212,992 |
| Logic Array Blocks (LABs) | 16,640 |
| User I/O Pins | 502 |
| Dedicated Inputs | 4 |
| Total Terminals | 672 |
| Package | 672-ball PBGA (FineLine BGA, 1.0 mm pitch) |
| Package Code (JEDEC) | S-PBGA-B672 |
| Core Supply Voltage (VCCINT) | 2.5 V nominal (2.375 V to 2.625 V) |
| Process Technology | CMOS |
| Propagation Delay | 2.5 ns |
| Speed Grade | -1 |
| Operating Temperature | Industrial (per 'I' suffix) |
| MSL Level | 3 |
| Peak Reflow Temperature | 220 C |
EP20K400FI672-1 s-pbga-b672 Pin Configuration Guide
Pin configuration for EP20K400FI672-1 (s-pbga-b672 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-1.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-1 is suitable for 6 applications: Telecom Switching Fabric (ATM / SONET), ASIC Prototyping and Logic Emulation, High-Speed Datapath / DSP Pre-Processing, PCI / PCI-X Bus Bridge and I/O Concentrator, Industrial Control / Machine Vision Front-End, Legacy Telecom Line Card / DSLAM Aggregation.
Telecom Switching Fabric (ATM / SONET)
The EP20K400FI672-1's 212,992 logic elements and 502 user I/O are well matched to telecom switching-fabric designs where wide parallel datapaths must be processed at line rates up to 155 MHz (STM-1/OC-3) and even 622 MHz (STM-4/OC-12) with careful pipelining. With 16,640 LABs and ESB-based dual-port RAM blocks, the device absorbs cell-header parsing, queue management, and pointer-adjustment state machines without external memory, dropping BOM cost and latency. The industrial temperature grade ('I' suffix) suits central-office deployments. PCB escape routing for the 672-ball PBGA at 1.0 mm pitch demands 4 mil trace-and-space and microvia stackups; engineers should reference Altera's AN123 APEX-20K hardware design guide for switch-fabric reference schematics.
Recommended
ASIC Prototyping and Logic Emulation
With 400K typical gates and 502 I/O, the EP20K400FI672-1 functions as a multi-million-gate ASIC prototype vehicle, partitioning a target ASIC into 4-6 APEX-20K devices using TDM-based multi-FPGA emulation. The device's ESBs supply on-chip dual-port RAM that maps ASIC register files and FIFOs at near-ASIC speed, and its industrial temperature grade lets the emulator chassis operate without aggressive cooling. Designers target a 30-50 MHz ASIC-equivalent clock rate, which is acceptable for software validation, while preserving ASIC-level signal visibility at full speed. Bring-up typically uses Quartus II with the MAX device support library; compile time for a fully utilized EP20K400 is 1-3 hours on a contemporary workstation.
Recommended
High-Speed Datapath / DSP Pre-Processing
The EP20K400FI672-1's LAB-rich architecture and embedded ESBs are well suited to fixed-point DSP pre-processing - FIR filters, FFT butterflies, and Reed-Solomon codecs - that feed an external DSP or host processor. With 16,640 LABs the device can host 64 to 128 parallel multiplier-accumulator slices at 80-120 MHz, enough to pre-process one channel of a 100 Mbps packet stream. The 502 I/O let the FPGA stream data into external DDR SDRAM, link-layer devices, and QDR SRAM in parallel without bus multiplexing. Quartus II's MegaWizard generates parameterized FIR and FFT cores targeting APEX-20K ESB memories, avoiding manual hand-coding of distributed-RAM coefficient tables.
Recommended
PCI / PCI-X Bus Bridge and I/O Concentrator
The 502 user I/O make the EP20K400FI672-1 a natural PCI/PCI-X bridge that connects a host CPU to legacy peripherals, PMC modules, and custom parallel buses. The device's 32-bit/64-bit PCI core supports 33 MHz and 66 MHz operation, and its ESBs implement the FIFOs that absorb burst traffic between the PCI bus and the application logic. The -1 speed grade provides comfortable timing margin at 66 MHz PCI-X, while the industrial temperature grade suits factory-floor and outdoor enclosures. PCI-compliance pre-silicon checklist requires 4-layer PCB with controlled-impedance 65 ohm traces and proper REQ/GNT sideband routing - engineers should reference Altera's PCI reference design bundled with Quartus II.
Recommended
Industrial Control / Machine Vision Front-End
Industrial machine-vision systems often pair the EP20K400FI672-1 with a CMOS image sensor, an LVDS deserializer, and a frame grabber to perform real-time Bayer-to-RGB conversion, edge detection, and region-of-interest cropping before passing frames to a host CPU. The 502 I/O are sufficient to ingest four parallel LVDS channels plus GPIO for trigger/encoder inputs, while the 212,992 logic elements handle Sobel/Prewitt kernels and histogram accumulation. The industrial temperature grade allows operation in factory enclosures up to +85 C, and the device's CMOS core draws modest quiescent current for fan-less vision controllers. Quartus II's OpenCL and DSP Builder toolflows accelerate the vision pipeline design by 3-5x versus hand-coded VHDL.
Recommended
Legacy Telecom Line Card / DSLAM Aggregation
DSLAM line cards aggregating 24 to 48 ADSL2+/VDSL2 channels over an STM-1 uplink can use the EP20K400FI672-1 as a multi-channel framer, interleaver, and Reed-Solomon codec engine. The 502 I/O accept parallel DSL PHY data from multiple line-driver chips, and the ESBs implement the convolutional interleaver memory required by ADSL2+ standard. Industrial temperature operation suits outdoor DSLAM cabinets, while the -1 speed grade meets the latency budget for the ADSL2+ fast-path interleaving. Lifecycle risk is real - new designs should evaluate the APEX-20K's Cyclone IV GX successor for any greenfield deployment, but maintenance contracts and brownfield line-card refreshes continue to use the EP20K400FI672-1.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFI672-2X | EP20K400EFI672-2N | EP20K400EFC672-1 | EP20K400EFC672-3 | EP20K400EBC652-1 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-ball PBGA (1.0 mm pitch) | 672-ball PBGA - same | 672-ball PBGA - same | 672-ball PBGA - same | 672-ball PBGA - same | 652-ball BGA - family compatible |
| Logic Elements | 212,992 | 212,992 - same | 212,992 - same | 212,992 - same | 212,992 - same | 212,992 - same |
| Typical Gates | 400,000 | 400,000 - same | 400,000 - same | 400,000 - same | 400,000 - same | 400,000 - same |
| User I/O | 502 | 502 - same | 502 - same | 502 - same | 502 - same | ~488 (652-ball variant) |
| Core Voltage | 2.5 V (2.375-2.625 V) | 2.5 V - same | 2.5 V - same | 2.5 V - same | 2.5 V - same | 2.5 V - same |
| Speed Grade | -1 | -2 | -2 | -1 | -3 | -1 |
| Temperature Range | Industrial (-40 C to +85 C) | Industrial | Industrial | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) |
Key Differentiators
- Industrial temperature grade in the 672-ball PBGA package (vs EP20K400EFC672-1)
- Highest -1 speed grade within the APEX-20K 400K PBGA family (vs EP20K400EFI672-2X)
- Same logic density with finer package option (vs EP20K400EBC652-1)
Design Notes
The EP20K400FI672-1's 672-ball PBGA at 1.0 mm pitch requires a 4-layer or 6-layer PCB with microvia (laser-drilled) stackup. Per Altera's APEX-20K hardware design guide (AN123), allocate 4 mil (0.1 mm) trace width and 4 mil space for escape routing on the top layer, with 8 mil vias in a dog-bone fanout pattern. Use a continuous GND plane on layer 2 directly under the BGA to provide a low-impedance return path; VCCINT and VCCIO planes should be on layers 3 and 4. Decoupling: one 0.1 µF X7R ceramic per VCCINT/VCCIO ball pair, plus 4.7 µF and 22 µF tantalum bulk capacitors every 25-30 balls. Power-plane islands should be stitched with 0.3 mm vias on a 1.5 mm grid to suppress resonance above 1 GHz. Estimated: with the standard escape pattern above, a single 672-ball PBGA consumes approximately 20×20 mm of top-layer real estate for breakout plus via fanout.
Power sequencing on the EP20K400FI672-1 must follow the APEX-20K datasheet: VCCINT (2.5 V core) must reach its 2.375 V minimum before any VCCIO rail rises, and VCCIO must not exceed VCCINT by more than 3.6 V at any time (or VCCINT damage may result). Use a power-supply supervisor (e.g., TPS3808) to enforce the 100 ms monotonic ramp and to gate the nCONFIG signal until both rails are stable. Quiescent current for an empty bitstream is approximately 50 mA on VCCINT plus I/O contribution proportional to toggle rate - at 50% utilization and 100 MHz, expect 600 mA to 1200 mA on VCCINT. Place a 22 µF X5R bulk capacitor adjacent to the VCCINT balls and a 10 µF X5R adjacent to each VCCIO bank. Estimated: a fully-utilized EP20K400FI672-1 at 100 MHz typically draws 1.5 W to 3 W of core power depending on clock tree utilization.
The 502 user I/O on the EP20K400FI672-1 are organized into banks that share a VCCIO rail - mixing incompatible I/O standards in the same bank requires a level-shifter or split-rail design. SSTL-2 and LVTTL cannot coexist in the same bank. According to the APEX-20K datasheet, the LVDS I/O option is only available in select banks; check the pinout table for bank assignments before committing the PCB layout. For clock distribution, use the dedicated DCLK/DCLKn pins routed with 100 ohm differential impedance; keep the clock trace length matched to within 50 mil of any secondary clock-distribution buffer. SSO (simultaneously-switching output) noise analysis is recommended at 32+ outputs switching simultaneously - derate the bank by 10-15% if SSO exceeds 32.
Common pitfalls with the EP20K400FI672-1 include: (1) attempting to use the legacy Altera ByteBlasterMV with a modern USB-Blaster cable without the APEX-20K configuration dongle - some 5th-party JTAG clones do not generate the 5 MHz TCK correctly; (2) forgetting that the MSEL[2:0] pins must be tied to the correct logic level for the chosen configuration mode (AS, AP, PS, JTAG) - leaving them floating causes intermittent configuration failure; (3) using a 3.3 V VCCIO without level translation on the JTAG chain, which can damage the device's 5 V-tolerant inputs over time; (4) ignoring the device's 2.5 ns propagation delay in the -1 speed grade and over-constraining timing paths that Quartus then fails to close. Verify the configuration mode strapping and JTAG chain integrity before debugging logic failures.
Compliance Information
Compliance status was not present in the verified web data; RoHS / lead-free status must be requested as a Certificate of Conformance from the distributor at order entry because the APEX-20K family predates widespread RoHS adoption. AEC-Q100 is not applicable because this is an FPGA for industrial/commercial markets, not automotive-grade.
