EP20K400FI672-1XN - APEX 20K FPGA 400K Gates BGA-672 | Intel
MPN: EP20K400FI672-1XN ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP20K400FI672-1XN Overview
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated I/O cells. FPGAs are designed to be reconfigured by the customer after manufacture, allowing engineers to implement custom digital logic, state machines, glue logic, DSP pipelines, and even soft processor cores on a single silicon device. They sit within the broader taxonomy of programmable logic -> logic ICs -> integrated circuits, alongside CPLDs, PALs, and GALs. APEX 20K was Intel/Altera's first family to merge Look-Up Table (LUT) based logic with embedded memory blocks, predating the modern Stratix and Cyclone series.
Key features include 16,640 logic elements (LEs), approximately 400,000 typical gates, 212 Kbits of embedded SRAM, four Phase-Locked Loops (PLLs) for clock management, and support for LVDS and PCI I/O standards. The device offers up to 488 user I/O pins, allowing direct interfacing with high-pin-count peripherals, memory buses, and backplane connectors. MultiVolt I/O compatibility allows the part to bridge 2.5 V core logic with 3.3 V or 5 V-tolerant external signals, simplifying mixed-voltage board designs.
The EP20K400FI672-1XN uses a SRAM-based configuration cell, meaning the device must be reconfigured at every power-up from an external PROM (typically EPC16 or EPC8) or via JTAG. The built-in JTAG (IEEE 1149.1) boundary-scan interface simplifies board-level testing and in-system programming. The four on-chip PLLs provide clock multiplication, division, phase shifting, and duty-cycle control, which is critical for source-synchronous interfaces such as DDR memory controllers and LVDS links.
Typical applications include telecommunications line cards, high-speed image and video processing pipelines, ASIC prototyping, DSP co-processing in wireless base stations, and industrial control systems that demand high logic density. The wide I/O count also makes the device suitable for legacy PCI bus bridges and custom parallel backplane glue logic. Designers typically use the Quartus II or MAX+PLUS II development environment for synthesis, place-and-route, and bitstream generation.
When designing with this device, note that the FineLine BGA-672 package requires a multi-layer PCB with microvia or via-in-pad technology for reliable assembly, and that the part is a legacy / NRND product in Intel's FPGA portfolio. Customers should verify long-term supply availability and consider migrating to a Cyclone, Stratix, or newer Agilex device for new designs. The JTAG configuration chain should be protected by appropriate ESD and series-termination on TCK/TMS lines.
Drop-in alternatives for EP20K400FI672-1XN — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-1XN (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Series, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FI672-1X
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400FI672-1N
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View Datasheet →EP20K400FI672-1
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View Datasheet →EP20K400EFC672-1XN
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View Datasheet →EP20K400EFC672-1N
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$175 / Unit
View Datasheet →EP20K400EFC672-1
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View Datasheet →EP20K400EFI672-2X
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View Datasheet →EP20K400FI672-1XN Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Device | EP20K400 |
| Typical Gates | 400,000 |
| Logic Elements | 16,640 |
| Maximum User I/O Pins | 488 |
| Embedded System Memory | 212 Kbit |
| Number of PLLs | 4 |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | 2.5 V / 3.3 V |
| Process Technology | 0.18 micrometer CMOS |
| Package | 672-ball FineLine BGA (FI672) |
| Package Size | 27 mm x 27 mm |
| Operating Temperature | -40 C to +85 C (industrial) |
| Configuration Method | SRAM, JTAG, EPC serial PROM |
| JTAG Support | IEEE 1149.1 boundary-scan compliant |
| Speed Grade | -1 |
| MSL Level | 3 |
EP20K400FI672-1XN Pin Configuration
| Pin A1 | I/O — General-purpose user I/O (bank 1) |
| Pin B1 | I/O — General-purpose user I/O (bank 1) |
| Pin C1 | VCCIO — I/O supply voltage (2.5 V / 3.3 V) |
| Pin D1 | GND — Ground |
| Pin E1 | I/O — General-purpose user I/O (bank 2) |
| Pin F1 | I/O — General-purpose user I/O (bank 2) |
| Pin G1 | VCCINT — Core supply voltage (2.5 V) |
| Pin H1 | I/O — General-purpose user I/O (bank 3) |
| Pin J1 | I/O — General-purpose user I/O (bank 3) |
| Pin K1 | GND — Ground |
Typical Applications
EP20K400FI672-1XN is suitable for 6 applications: Telecommunications Line Cards, ASIC Prototyping and Logic Emulation, High-Speed Image and Video Processing, Industrial Control and Factory Automation, PCI Bus Bridges and Legacy I/O Expansion, DSP Co-Processing in Wireless Baseband.
Telecommunications Line Cards
The EP20K400FI672-1XN is well-suited for legacy telecom line cards that require 400K gates of glue logic and 488 user I/O pins to bridge multiple E1/T1 framers, HDLC controllers, and time-division multiplexing backplanes. With 4 on-chip PLLs, the FPGA can generate the multiple reference clocks required for TDM bus synchronization while its 212 Kbits of embedded system memory provides per-channel elastic buffers and lookup tables. The BGA-672 footprint packs this density into a footprint that fits standard ATCA/AMC line-card area, and the -1 speed grade is fast enough for 77.76 MHz STS-1 / 155 MHz STS-3 backplane operation without external clock-recovery devices.
Recommended
ASIC Prototyping and Logic Emulation
The EP20K400FI672-1XN delivers approximately 400,000 system gates, which historically made it a popular vehicle for ASIC and ASSP prototyping before the Stratix and Cyclone families were introduced. Engineers can map multi-million-gate ASICs onto a small array of APEX 20K devices, validating RTL, running real-world firmware, and verifying system timing before committing to silicon. The 16,640 logic elements support wide datapath and control logic, while the 488 I/O pins let the prototype connect to DDR memory, PCI peripherals, and application-specific I/O. The JTAG-based configuration allows rapid bitstream reloads during bring-up, dramatically shortening verification cycles compared to mask-set ASIC spins.
Recommended
High-Speed Image and Video Processing
The 16,640 logic elements and 212 Kbits of embedded system memory make the EP20K400FI672-1XN well matched to image-processing pipelines such as real-time video scaling, color-space conversion, and edge detection in industrial cameras and broadcast equipment. The FPGA can ingest parallel RGB / YCbCr video streams at 100 MHz+ using LVCMOS or LVDS I/O and perform per-pixel computations without off-chip buffering for line-sized images. The 488 user I/O pins allow direct connection to video ADCs/DACs, frame buffers, and FPGA-to-FPGA expansion links. Designers benefit from the device's four PLLs for generating independent pixel, memory, and expansion clocks from a single reference.
Recommended
Industrial Control and Factory Automation
With 488 I/O pins and industrial temperature grade (-40 C to +85 C), the EP20K400FI672-1XN is well suited for PLC backplanes, motor-control boards, and factory-automation controllers that require a large number of discrete and bus-driven signals. The FPGA can implement custom fieldbus bridges (Profibus, Modbus, EtherCAT slave logic), encoder counters, and PWM generators in a single device, replacing multiple CPLDs and discrete logic. The 2.5 V core and 3.3 V I/O supplies align with industrial 24 V->5 V->3.3 V power trees, and the BGA-672 package supports reflow-compatible assembly on multi-layer FR-4 PCBs typical in industrial hardware.
Recommended
PCI Bus Bridges and Legacy I/O Expansion
Recommended
DSP Co-Processing in Wireless Baseband
The EP20K400FI672-1XN pairs 16,640 logic elements with 212 Kbits of dedicated SRAM, providing enough logic density for baseband channel cards in early-2000s GSM / CDMA base stations to host custom DSP acceleration blocks (FIR filters, correlators, Viterbi decoders) alongside the host ASIC or DSP. The SRAM blocks serve as coefficient storage and tap delay lines, and the 4 PLLs generate the multiple baseband / IF / clock-recovery frequencies required by the radio chain. Although the part has been superseded by modern SoCs and DSP+FPGA SoCs, it remains in service in long-lifecycle defense and infrastructure programs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-1XN — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FI672-1X | EP20K400EFC672-1XN | EP20K400EFI672-2X |
|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | BGA-672 (FineLine, 27x27 mm) | BGA-672 (FineLine) - same | BGA-672 (FineLine) - same | BGA-672 (FineLine) - same |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 |
| Typical Gates | 400,000 | 400,000 | 400,000 | 400,000 |
| Embedded Memory | 212 Kbit | 212 Kbit | 212 Kbit | 212 Kbit |
| Speed Grade | -1 (fastest) | -1 | -1 | -2 (slower) |
| Temperature Grade | Industrial (-40 C to +85 C) | Industrial | Industrial | Industrial |
| Pricing (USD, qty 1) | 285.00 | ~280.00 | ~290.00 | ~260.00 |
Key Differentiators
- Industrial temperature grade at the fastest -1 speed grade (vs EP20K400EFC672-1 (commercial temperature))
- Drop-in identical ball map with sibling APEX 20K variants (vs EP20K400EFI672-2X (same family, -2 speed grade))
- Wide 488 user I/O count for bus-bridging applications (vs EP20K400FG672-2 (different package, FPG package))
Design Notes
Estimated: at 100% toggle rate across 16,640 logic elements at 100 MHz, the EP20K400FI672-1XN can dissipate up to 2-3 W. The FineLine BGA-672 has a typical theta_JA around 12-15 C/W on a 4-layer JEDEC test board, so junction temperature rise is roughly 25-45 C above ambient. For enclosed industrial enclosures with restricted airflow, place thermal vias under the central BGA power grid and consider a heat spreader to keep Tj below 125 C. Use the Quartus II PowerPlay analyzer for accurate per-design power estimates.
The 672-ball FineLine BGA requires a multi-layer PCB (minimum 6 layers recommended) with 0.4 mm to 0.5 mm ball pitch. Use microvia or via-in-pad technology to fan out the inner balls. Decouple each VCCINT pin with a 0.1 uF X7R ceramic placed within 50 mils of the ball, and bulk-decouple each power rail with a 10 uF to 22 uF tantalum or polymer capacitor. Maintain a solid VCCINT and GND plane under the device to minimize power-supply inductance and IR drop.
Do not leave any VCCINT or VCCIO ball floating - the APEX 20K family requires all power balls to be connected for proper operation. Ensure MSL 3 moisture-sensitive handling is followed (floor life 168 hours at < 30 C / 60 % RH) or bake the parts before assembly. The SRAM-based configuration means the FPGA loses its design on every power-down - a configuration PROM (EPC8 or EPC16) is mandatory unless the design is always reprogrammed via JTAG at startup.
Assign high-speed I/O (LVDS, clock inputs) to the dedicated clock and PLL-adjacent balls before generic I/O to ease timing closure. Keep all four PLL analog supply pins (VCC_PLL) isolated from digital VCCINT with a ferrite bead or filter and bypass with a 0.1 uF + 10 uF capacitor network to minimize jitter. Route JTAG TCK/TMS with 33 ohm series termination and avoid routing them adjacent to fast-edge I/O to prevent false triggers during boundary-scan.
Compliance Information
RoHS / REACH / lead-free / halogen-free status for EP20K400FI672-1XN was not explicitly listed in the verified web data and is marked unknown. The 'N' suffix on the related EP20K400FI672-1N and EP20K400EFC672-1N parts indicates Pb-free ball variants per APEX 20K ordering information, so engineers should request a Certificate of Compliance from the specific supplier for the lot they are purchasing.
