EP20K400FI672-1X - APEX 20K 400K-Gate FPGA, 672-BGA | Intel
MPN: EP20K400FI672-1X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $145 | $14,500.00 |
| 500 | $125 | $62,500.00 |
| 1,000 | $110 | $110,000.00 |
EP20K400FI672-1X Overview
An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement custom digital logic by configuring an array of configurable logic blocks (CLBs), interconnect, and I/O cells after manufacture. FPGAs sit within the broader hierarchy of programmable logic -> logic IC -> integrated circuit -> semiconductor, offering higher density and performance than CPLDs while remaining reconfigurable in-system, unlike ASICs. The APEX 20K architecture pioneered multi-core integration by combining logic, memory, and I/O on a single die optimized for system-on-a-chip (SoC) prototyping and high-bandwidth datapaths.
Key features include 16640 logic elements, 212,992 RAM bits, 488 maximum user I/O, and 4 dedicated inputs. The device operates with a nominal core supply of 2.5 V (range 2.375 V to 2.625 V) and supports I/O standards via selectable VCCIO banks. The speed grade "-1X" denotes an enhanced commercial speed bin. The 672-BGA package provides a 27 x 27 mm substrate area suitable for high-density board designs requiring maximum pin count.
Architecturally, the EP20K400 employs the APEX 20K multi-core structure: MegaLAB blocks each contain 16 LABs, 1 EAB (Embedded Array Block) of 2,048 bits plus RAM/ROM functions, plus MegaLAB interconnect. Configuration is via serial or parallel PROM or in-system via JTAG. PLLs are not present; clock management relies on dedicated clock inputs and DLLs.
Typical applications include telecommunications line cards, ASIC prototyping, custom datapath acceleration, video processing, and high-speed bus interfaces. The APEX 20K family supports PCI, LVDS, SSTL, GTL+, and other I/O standards when paired with appropriate VCCIO levels.
When designing with this part, verify that VCCINT and VCCIO rails meet 2.5 V and the selected I/O standard respectively. Unused I/O pins must be configured per the Quartus/MAX+PLUS II documentation to avoid leakage. This page synthesizes distributor pricing, drop-in same-package alternatives, and design considerations that are not consolidated in the manufacturer datasheet.
Drop-in alternatives for EP20K400FI672-1X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-1X (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, Family, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFC672-1XN
✅ Drop-In✓ In Stock
$215 / Unit
View Datasheet →EP20K400EFC672-1
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400EFI672-2X
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP20K400EFI672-2N
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EP20K400EFC672-1N
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K400FI672-1X Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Logic Elements | 16640 |
| Typical Gates | 400000 |
| Embedded Memory (bits) | 212992 |
| Maximum User I/O | 488 |
| Dedicated Inputs | 4 |
| Number of Terminals | 672 |
| Package | 672-BGA (FineLine BGA, 27 x 27 mm) |
| Terminal Form | Ball |
| Package Code | BGA |
| Package Shape | Square |
| Nominal Core Voltage (VCCINT) | 2.5 V |
| VCCINT Range | 2.375 V to 2.625 V |
| Speed Grade | -1X |
| Mounting Type | Surface Mount |
| Process Technology | CMOS |
| MSL Level | 3 |
| Peak Reflow Temperature | 220 C |
EP20K400FI672-1X square Pin Configuration Guide
Pin configuration for EP20K400FI672-1X (square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-1X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-1X is suitable for 6 applications: Telecommunications Line Card Logic, ASIC Prototyping and Emulation, Video and Image Processing Pipelines, High-Speed Datapath Acceleration, Industrial Control and Legacy I/O Expansion, Legacy Avionics and Defense Upgrades.
Telecommunications Line Card Logic
The EP20K400FI672-1X delivers 400,000 gates of reconfigurable logic in a 672-BGA, ideal for telecom line cards implementing ATM cell processing, HDLC framing, and protocol bridging. Its 212,992 bits of embedded dual-port RAM provide per-channel FIFOs and lookup tables without external SRAM. The 488 user I/Os support wide parallel buses to network processors, while 2.5 V VCCINT plus selectable VCCIO banks enable direct interface to 3.3 V PCI, 2.5 V LVCMOS, and 5 V-tolerant buses through external resistor dividers. APEX 20K Cascade support also lets the EP20K400 expand as a co-processor to a host APEX 20KE.
Recommended
ASIC Prototyping and Emulation
Engineers use the EP20K400FI672-1X as an ASIC prototype vehicle because 400K gates with 212 Kbits of distributed memory map well to mid-density ASICs and pre-silicon validation flows. The MultiVolt I/O and JTAG-based in-system programming let designers iterate RTL before tap-out without re-spinning boards. Although newer Cyclone/Stratix families supersede it, thousands of long-lifecycle ASIC prototypes still rely on APEX 20K because the bitstream and board files are frozen and qualified.
Recommended
Video and Image Processing Pipelines
With 16640 logic elements, 212 Kbits of embedded RAM, and 488 I/O pins, the EP20K400FI672-1X fits mid-resolution video pipelines such as SD-SDI multiplexers, deinterlacers, and color-space converters. The MegaLAB architecture provides distributed memory blocks ideal for line buffers and small frame stores. Designers pair the EP20K400 with external SDRAM for larger frames while using internal EABs for pixel-rate FIFO and lookup-table operations.
Recommended
High-Speed Datapath Acceleration
The 672-BGA EP20K400FI672-1X implements wide datapath accelerators such as CRC engines, Reed-Solomon codecs, and bus-width converters thanks to its 488 I/Os and 16-bit MegaLAB-aligned routing. Embedded EABs deliver 2,048-bit synchronous RAM blocks per cluster, enabling pipelined register files and coefficient ROMs. Designers targeting >100 MHz datapaths should choose speed grade -1X (this part) over -2/-3 variants for timing margin.
Recommended
Industrial Control and Legacy I/O Expansion
The industrial-temperature (I-suffix) variant EP20K400FI672-1X, or its sibling EP20K400EFI672-2X, supports long-lifecycle industrial controllers where PC/104, ISA, and parallel-CNC bus interfaces must be reconstructed. The 488 I/Os and MultiVolt banks allow direct connection to 5 V and 3.3 V peripheral buses. Because APEX 20K is mature and well-documented, repair and field-replacement boards for legacy machinery remain in demand for decades.
Recommended
Legacy Avionics and Defense Upgrades
Defense and avionics platforms designed in the late 1990s and 2000s still contain EP20K400FI672-1X-based boards, and obsolescence-management programs must source drop-in same-package replacements. The 672-BGA footprint is shared across the APEX 20K and APEX 20KE 400K-gate family, so EP20K400EFC672-1X / -2 / -2X variants can be substituted without reworking the PCB. Modernization programs typically migrate to Cyclone IV/V or Microsemi/Microchip IGLOO2 equivalents, but drop-in replacements keep existing hardware airworthy during transition.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-1X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFC672-1X | EP20K400EFC672-1 | EP20K400EFC672-2 | EP20K400EFI672-2X |
|---|---|---|---|---|---|
| Package | 672-BGA (27 x 27 mm) | 672-BGA - same footprint | 672-BGA - same footprint | 672-BGA - same footprint | 672-BGA - same footprint |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | APEX 20K | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20KE |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 |
| Embedded Memory (bits) | 212992 | 212992 | 212992 | 212992 | 212992 |
| Maximum User I/O | 488 | 488 | 488 | 488 | 488 |
| Speed Grade | -1X | -1X | -1 | -2 | -2X |
| VCCINT | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Industrial Temp (I-suffix) | No | No | No | No | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Same 400K-gate density, enhanced APEX 20KE core (vs EP20K400EFC672-1X)
- Industrial temperature grade available in same footprint (vs EP20K400EFI672-2X)
- Lead-free N-suffix variant for environmental compliance (vs EP20K400EFC672-1N)
Design Notes
The EP20K400FI672-1X requires a tightly regulated 2.5 V VCCINT rail capable of delivering up to ~1.5 A at full utilization (estimated: ICCINT max at 400K-gate utilization is approximately 0.6-1.5 A depending on toggle rate). Place 100 uF bulk + 0.1 uF + 0.01 uF decoupling on each VCCINT ball cluster; the 672-BGA package has multiple VCCINT/VSS pairs that must all be connected. VCCIO banks must each be supplied independently to support mixed-voltage I/O standards such as 3.3 V PCI and 2.5 V LVCMOS on the same die.
The 672-BGA FineLine package has a 1.0 mm ball pitch (typical for APEX 20K FI variants). PCB design must use 4 or 6 metal layers with microvia-in-pad or laser-drilled stacked vias to break out the BGA fanout. All balls require dog-bone or via-in-pad fanout with matched impedance control on high-speed LVDS/GTL+ traces. Use the Intel/Altera APEX 20K package footprint file from the device pin table to ensure exact ball-pad diameter and mask opening are observed.
Do not load an APEX 20K bitstream into an APEX 20KE device (or vice versa) - the configuration architectures differ and the device will not function correctly. Always verify configuration mode pins (MSEL) match the chosen EPC configuration PROM. Unused I/O pins must be set as inputs with bus-hold or as outputs driving defined values per MAX+PLUS II/Quartus recommendations to avoid shoot-through current. JTAG chain order must include any boundary-scan devices in the documented TDI->TDO sequence.
Estimated junction-to-ambient thermal resistance (theta_JA) for the 672-BGA with a JEDEC-standard 4-layer test board is approximately 12-18 C/W. At 1 A VCCINT current and 2.5 V supply, internal power dissipation is ~2.5 W at maximum utilization, yielding a junction temperature rise of ~30-45 C above ambient. For high-utilization designs in enclosed enclosures, attach a heatsink or thermal pad to the package top and ensure adequate airflow.
Compliance Information
Part is obsolete; current Intel/Altera documentation does not maintain a definitive RoHS/REACH statement. Treat compliance fields as unknown unless the specific distributor lot is certified.
