EP20K400EFI672-2X - 400K-Gate APEX 20KE FPGA, 672-FBGA | Intel
MPN: EP20K400EFI672-2X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $262.5 | $2,625.00 |
| 100 | $228 | $22,800.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $168 | $168,000.00 |
EP20K400EFI672-2X Overview
An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows designers to configure logic resources and interconnects after manufacturing. Within the broader semiconductor taxonomy, FPGAs sit between standard logic ICs and ASICs: more flexible than fixed-function chips but lower per-unit cost than full-custom ASICs at low volumes. The APEX 20KE family specifically introduced MultiCore architecture that pairs fine-grain LUT logic with coarse-grain EAB memory, enabling SOPC integration of processors, memory and I/O on a single programmable fabric.
Key features of the EP20K400EFI672-2X include 16,640 logic elements organized into Logic Array Blocks (LABs), 212,992 bits of RAM, 480 LVTTL/LVCMOS-compatible I/O organized into 8 I/O banks, four Phase-Locked Loops (PLLs) for clock management, and support for multiple I/O standards including LVTTL, LVCMOS, PCI and GTL+. The part is specified for the industrial 0 °C to 85 °C operating temperature range with a 1.71 V to 1.89 V core supply tolerance.
Technically, the MultiCore architecture allows each logic element to operate as a 4-input LUT, a 16-bit shift register, or a small memory block, while EABs provide up to 2,048 bits each of synchronous dual-port RAM, ROM or content-addressable memory. The four embedded PLLs multiply, divide and phase-shift incoming clocks up to 223 MHz, eliminating off-chip clock generators in many designs. The 672-pin FineLine BGA package is a 27 mm × 27 mm FC-FBGA with 1.27 mm pitch that supports high-speed board designs with controlled-impedance signal paths.
Typical applications include telecommunications line cards, industrial control and automation backplanes, high-speed data-acquisition front-ends, military/aerospace signal processing prototypes, and PCI-based I/O expansion cards. The combination of 488 user I/Os and 212,992 bits of embedded memory makes it well suited to designs that previously required a separate controller ASIC plus a discrete logic FPGA. Designers often pair the EP20K400EFI672-2X with external SDRAM and a microprocessor for embedded compute platforms.
When designing with this device, allocate at least 20 % of logic utilization as headroom for place-and-route closure, and verify that LVTTL/LVCMOS drive strength is matched to each signal path. Power sequencing requires VCCINT (1.8 V) to ramp before VCCIO to prevent I/O latch-up; consult the APEX 20KE datasheet for the recommended sequencing diagram. The part is in the mature/end-of-life phase of its lifecycle - confirm long-term availability with Intel/Altera distributors before committing to new designs.
This page synthesizes distributor pricing, drop-in APEX 20KE alternatives, comparison tables and design notes that are not found in a single datasheet, helping engineers quickly decide whether the EP20K400EFI672-2X fits their high-density programmable-logic application.
Drop-in alternatives for EP20K400EFI672-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400EFI672-2X (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Speed Grade, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFC672-2X
✅ Drop-In✓ In Stock
$118.9 / Unit
View Datasheet →EP20K400EFC672-1XN
✅ Drop-In✓ In Stock
$215 / Unit
View Datasheet →EP20K400EFC672-2N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-3N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K300EFI672-2X
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFI672-2X Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Series | EP20K400E |
| Logic Elements | 16,640 |
| System Gates | 400,000 |
| Embedded Memory | 212,992 bits |
| Maximum User I/O | 488 |
| Number of I/O Banks | 8 |
| PLLs | 4 |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V nominal) |
| Process Technology | 0.22 µm CMOS |
| Maximum Internal Frequency | 223 MHz |
| Operating Temperature | 0 °C to 85 °C (Industrial) |
| Package | 672-ball FineLine BGA (FC-FBGA), 27 × 27 mm |
| Ball Pitch | 1.27 mm |
| Mounting Type | Surface Mount |
| Moisture Sensitivity Level (MSL) | 3 |
| Peak Reflow Temperature | 220 °C |
| Halogen Free | Compliant |
| RoHS Status | Compliant |
EP20K400EFI672-2X Pin Configuration
| Pin A1 | I/O — User I/O (bank 1, LVTTL/LVCMOS/PCI/GTL+) |
| Pin B2 | I/O — User I/O (bank 1, LVTTL/LVCMOS/PCI/GTL+) |
| Pin C3 | I/O — User I/O (bank 1, LVTTL/LVCMOS/PCI/GTL+) |
| Pin D4 | I/O — User I/O (bank 2, LVTTL/LVCMOS/PCI/GTL+) |
| Pin E5 | I/O — User I/O (bank 2, LVTTL/LVCMOS/PCI/GTL+) |
| Pin F6 | I/O — User I/O (bank 3, LVTTL/LVCMOS/PCI/GTL+) |
| Pin G7 | I/O — User I/O (bank 3, LVTTL/LVCMOS/PCI/GTL+) |
| Pin H8 | I/O — User I/O (bank 4, LVTTL/LVCMOS/PCI/GTL+) |
| Pin J9 | I/O — User I/O (bank 4, LVTTL/LVCMOS/PCI/GTL+) |
| Pin K10 | I/O — User I/O (bank 5, LVTTL/LVCMOS/PCI/GTL+) |
| Pin L11 | I/O — User I/O (bank 5, LVTTL/LVCMOS/PCI/GTL+) |
| Pin M12 | I/O — User I/O (bank 6, LVTTL/LVCMOS/PCI/GTL+) |
| Pin N13 | I/O — User I/O (bank 6, LVTTL/LVCMOS/PCI/GTL+) |
| Pin P14 | I/O — User I/O (bank 7, LVTTL/LVCMOS/PCI/GTL+) |
| Pin R15 | I/O — User I/O (bank 7, LVTTL/LVCMOS/PCI/GTL+) |
| Pin T16 | I/O — User I/O (bank 8, LVTTL/LVCMOS/PCI/GTL+) |
| Pin U17 | GND — Ground |
| Pin V18 | VCCINT — Core supply (1.71 V - 1.89 V) |
| Pin W19 | VCCIO1 — I/O bank 1 reference voltage |
| Pin Y20 | VCCIO8 — I/O bank 8 reference voltage |
Typical Applications
EP20K400EFI672-2X is suitable for 6 applications: Telecommunications Line Card, Industrial Control Backplane, High-Speed Data Acquisition Front-End, PCI Bus I/O Expansion Card, Military/Aerospace Signal Processing Prototype, Networked Storage Controller.
Telecommunications Line Card
The EP20K400EFI672-2X is well matched to telecom line cards because its 488 user I/O pins can interface directly with multi-channel framer ICs and backplane SERDES, while the 212,992 bits of embedded memory absorb packet buffering and lookup-table traffic without external SRAM. The four on-chip PLLs generate the multiple clock domains (TDM bus, fabric, and PHY) required by SDH/SONET and PDH framer designs. Designers place the device between the TDM framer and the network processor, using LVTTL/LVCMOS I/O banks for low-skew parallel interconnect. The industrial 0 °C to 85 °C temperature grade covers central-office deployments. Total I/O count and EAB-based packet memory are the decisive advantages over smaller APEX 20KE members.
Recommended
Industrial Control Backplane
In PLC backplane designs the EP20K400EFI672-2X provides 488 user I/O to drive dozens of optically-isolated 24 V digital inputs and outputs while running deterministic logic for motion control loops. The 16,640 logic elements implement IEC 61131-3 function-block runtimes plus custom motion trajectories, and the embedded EAB memory stores cam profiles and lookup tables for servo interpolation. Industrial 0 °C to 85 °C operation is essential for factory-floor enclosures. Pair the FPGA with isolated RS-485 transceivers and the design replaces a traditional PLC CPU plus I/O module stack. The 672-FBGA package and 1.8 V core simplify integration into 24 V industrial supplies.
Recommended
High-Speed Data Acquisition Front-End
The 212,992 bits of embedded EAB memory and the 223 MHz internal Fmax of the EP20K400EFI672-2X support waveform capture front-ends that buffer ADC samples before forwarding to a host processor. Designers typically pair the FPGA with a high-speed ADC such as a 14-bit 125 MSPS converter, using LVTTL/LVCMOS I/O banks to capture parallel data at full sample rate. The MultiCore architecture allows each logic element to act as a 4-input LUT or small memory, ideal for FIR filtering and digital down-conversion. The industrial temperature grade suits laboratory and field instrumentation. The combination of I/O count, EAB depth and Fmax gives a cost-effective alternative to dedicated DSP chips.
Recommended
PCI Bus I/O Expansion Card
The EP20K400EFI672-2X directly supports 32-bit/33 MHz PCI bus interfacing through its LVTTL I/O banks plus the APEX 20KE PCI-compliant I/O standard. The 16,640 logic elements implement the PCI target/master state machines, scatter-gather DMA engines and interrupt controllers, while the 488 user I/O lines drive the off-board expansion connectors. Industrial-grade operation suits servers and embedded systems installed in non-climate-controlled racks. The 672-FBGA package fits standard PCI/PCI-X full-length card outlines. PCI-X 66 MHz operation is possible at reduced utilization in the -2 speed grade, making the EP20K400EFI672-2X a mature PCI bridge solution.
Recommended
Military/Aerospace Signal Processing Prototype
The APEX 20KE family has been widely adopted in military and aerospace signal-processing prototypes where the EP20K400EFI672-2X serves as a flexible DSP replacement for FFT, FIR and QAM demodulator functions. The 212,992 bits of EAB memory act as coefficient and data buffers for parallel FFT pipelines, while the 223 MHz internal Fmax supports real-time baseband processing at IF sample rates. The industrial 0 °C to 85 °C operating range covers most MIL-STD-810 ground-benign environments. Designers use the 488 I/Os to interface with high-speed ADCs/DACs and the four PLLs to derive IF and baseband clocks from a single reference. The 672-FBGA package is compatible with ruggedized board-stacking schemes.
Recommended
Networked Storage Controller
In RAID and NAS controller cards the EP20K400EFI672-2X implements the XOR-acceleration engine, SAS/SATA link-layer state machines and embedded processor interface, offloading compute-intensive parity calculations from the host CPU. The 16,640 logic elements handle multiple concurrent XOR streams and the 212,992 bits of EAB memory buffer sector-sized data blocks. Eight independent I/O banks let the FPGA bridge between the host PCIe edge and multiple SATA/SAS PHYs without external bus-switching logic. The industrial temperature grade supports 24/7 operation in non-air-conditioned server closets. The 672-FBGA package is ideal for full-height, half-length storage controller cards.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400EFI672-2X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFC672-2X | EP20K400EFC672-1X | EP20K400EFC672-2N | EP20K400EFC672-3N | EP20K300EFI672-2X |
|---|---|---|---|---|---|---|
| Package | 672-ball FineLine BGA (FC-FBGA) | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 11,520 |
| System Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 300,000 |
| Embedded Memory (bits) | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 147,456 |
| Max User I/O | 488 | 488 | 488 | 488 | 488 | 488 |
| Max Internal Frequency | 223 MHz | 223 MHz | 180 MHz | 223 MHz | 148 MHz | 223 MHz |
| Operating Temperature | 0 °C to 85 °C (Industrial) | 0 °C to 70 °C (Commercial) | 0 °C to 85 °C (Industrial) | 0 °C to 70 °C (Commercial) | 0 °C to 70 °C (Commercial) | 0 °C to 85 °C (Industrial) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
Key Differentiators
- Highest-density APEX 20KE 672-FBGA member with industrial temperature grade (vs EP20K300EFI672-2X)
- Industrial 0-85 °C operating range (vs EP20K400EFC672-2X)
- -2 speed grade for tighter timing margin (vs EP20K400EFC672-3N)
Design Notes
Power sequencing is mandatory for the EP20K400EFI672-2X: ramp VCCINT (1.8 V) before VCCIO banks and ensure VCCIO never exceeds VCCINT + 0.3 V during power-up to avoid I/O latch-up. Use a tracked supply rail and decoupling network of 100 nF ceramic + 10 µF bulk per VCCINT pin and per VCCIO bank. At 100 MHz fabric activity and 50 % I/O toggle, plan for approximately 3-5 W dissipation; verify with the PowerPlay early power estimator in Quartus II before final layout.
Estimated: with 5 W total dissipation and a JEDEC-compliant 672-FBGA board thermal resistance of about 8-12 °C/W, junction temperature rise above ambient is 40-60 °C in still air. For industrial enclosures up to 60 °C ambient, design with a 1 oz copper inner plane and thermal vias under the die flag to keep Tj below 125 °C. Forced airflow is recommended above 70 °C ambient. Use the device's on-die thermal diode (when accessible via JTAG) for in-system validation.
Place 0.1 µF decoupling capacitors within 5 mm of every VCCINT and VCCIO pin pair and add 10 µF bulk capacitors on each supply rail near the BGA perimeter. Route all 488 user I/Os on inner signal layers with 50 Ω controlled-impedance traces for LVTTL/LVCMOS and 65 Ω for GTL+; keep matched-length groups within 50 mil for clock and DDR-style interfaces. Stitch the BGA field with a full GND plane directly under the package and use microvias to escape the inner rows of the 672-ball array. Maintain a continuous reference plane beneath all high-speed signals.
Use the I/O bank's reference voltage (VREF) pins when configuring GTL+ inputs; floating VREF causes threshold drift and intermittent failures. Keep high-speed clock traces away from asynchronous reset and JTAG signals, and apply series termination (22-33 Ω) on source-synchronous LVCMOS outputs longer than 50 mm. The four PLLs each require their own filtered analog VCCA supply (2.5 V) and a quiet ground; isolate PLL power islands from digital switching noise.
Do not exceed the maximum concurrent I/O toggle rate of 50 MHz per pin across the entire 672-FBGA - per-bank utilization limits apply and exceeding them risks VCCIO droop. Always regenerate the programming file after any pin assignment change because the Quartus II fitter re-routes internal logic. NRND lifecycle means last-time-buy windows can close with little notice - secure long-term supply before committing to new production runs. Confirm MSL-3 floor-life (168 hours) handling when re-baking sealed trays.
Compliance Information
RoHS compliant and halogen-free per Intel/Altera APEX 20KE product specifications (GlobalSpec 2026-09-08). AEC-Q100 not applicable - APEX 20KE is not an automotive-qualified family.
