EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
MPN: EP20K400FI672-3X ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $245 | $2,450.00 |
| 100 | $198 | $19,800.00 |
| 500 | $165 | $82,500.00 |
| 1,000 | $142 | $142,000.00 |
EP20K400FI672-3X Overview
Background: A field-programmable gate array (FPGA) is a semiconductor integrated circuit containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that an engineer can re-program in the field to implement arbitrary digital logic. FPGAs sit hierarchically under the broader category of programmable logic devices (PLDs) - alongside CPLDs and older PROMs/PALs - and above simple fixed-function ASICs in the digital IC taxonomy. The APEX 20K family, introduced by Altera in 1999, was among the first "system-on-a-programmable-chip" families combining embedded memory blocks and look-up-table logic with True-LVDS and PLL support, paving the way for modern SoC FPGAs.
Key features that distinguish the EP20K400FI672-3X include its 400K system-gate capacity, MultiCore architecture combining fine-grain logic elements with embedded array blocks (EABs) for on-chip memory, dedicated clock management with PLL blocks, JTAG boundary-scan support, and true 3.3 V/5 V tolerant I/O on selected banks. The '3' speed grade places it in the higher-performance tier of the family for the 672-pin BGA variant.
Technical depth: The -3X suffix indicates an industrial temperature range and the speed-grade 3 silicon; the device uses a CMOS SRAM configuration cell that must be loaded from an external configuration PROM or controller on every power-up. Compared with modern 7 nm FPGAs, the 400K-gate APEX 20K consumes substantially more static power and offers less DSP/serdes integration, but remains useful for legacy designs, long-life industrial systems, and cost-sensitive parallel-logic replacement.
Typical applications include telecommunications line cards, industrial motor control, legacy DSP preprocessing, military/aerospace upgrades of older designs, and ASIC prototyping. The wide I/O count (502) supports many parallel bus interfaces without external muxes.
Design consideration: Plan a robust configuration scheme (EPCS/Cyclone-style or legacy EPC2 PROM with JTAG fallback) because the SRAM-based APEX 20K loses configuration at every power cycle. Decouple each VCCINT/VCCIO plane with 0.1 uF plus 10 uF ceramic, and respect the 1.0 mm BGA pitch with via-in-pad or dog-bone fan-out for signal integrity on high-speed clocks.
This page synthesizes distributor pricing, drop-in alternatives from the same APEX 20K family, and practical design notes not found in the original Altera datasheet - useful for engineers maintaining long-life FPGA designs.
Drop-in alternatives for EP20K400FI672-3X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-3X (same form factor and footprint) — differing in Package, Process Technology, Speed Grade, Family, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FI672-3V
✅ Drop-In✓ In Stock
$285 / Unit
View Datasheet →EP20K400FI672-3N
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP20K400FI672-3
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400FI672-2X
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400FI672-1X
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400EFI672-2X
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP20K400FI672-3X Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Device Series | EP20K400 |
| Maximum System Gates | 400,000 |
| Maximum User I/O | 502 |
| Package | 672-ball Fine-Pitch BGA (S-PBGA-B672) |
| Terminal Pitch | 1.000 mm |
| Nominal Core Voltage (VCCINT) | 2.5 V |
| VCCINT Range | 2.375 V to 2.625 V |
| Typical Propagation Delay | 3.6 ns |
| Maximum Internal Clock Frequency | 833 MHz |
| Technology | CMOS SRAM configuration cell |
| Speed Grade | -3 (high-performance tier) |
| Temperature Grade (X suffix) | Industrial / extended |
| Moisture Sensitivity Level (MSL) | 3 |
| Peak Reflow Temperature | 220 C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (per Intel/Altera product page) |
EP20K400FI672-3X 672-ball fine-pitch bga (s-pbga-b672) Pin Configuration Guide
Pin configuration for EP20K400FI672-3X (672-ball fine-pitch bga (s-pbga-b672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-3X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-3X is suitable for 6 applications: Telecommunications Line Card Interface, Industrial Motor Control and Drive, Legacy ASIC Prototyping and Emulation, Military and Aerospace Avionics Upgrades, Medical Imaging Front-End Processing, Test and Measurement Instrumentation.
Telecommunications Line Card Interface
The EP20K400FI672-3X fits telecom line-card interface aggregation because its 502 user I/O lines can sink multiple T1/E1 framers, UTOPIA/POS-PHY buses, and parallel datapath converters in a single device, while the 833 MHz internal clock supports 155 Mbps POS-PHY Level-3 ingress. Industrial temperature grade ('X' suffix) tolerates the airflow-limited central-office environment where ambient can reach 55 C. The 2.5 V VCCINT keeps legacy 3.3 V LVCMOS peripherals attached without level shifters, and the JTAG TAP simplifies boundary-scan integration into factory test. Compared with newer Cyclone/Stratix families, the EP20K400's high I/O count at low unit cost remains attractive for mature line-card designs that must remain in production for 10-15 years.
Recommended
Industrial Motor Control and Drive
Motor-control and variable-frequency drive (VFD) designers choose the EP20K400FI672-3X for its high logic density combined with industrial-temperature reliability on the factory floor. The 672-BGA's high I/O count interfaces directly with multiple encoder inputs (QEP), 3-phase PWM timers, current-sense ADCs, and CAN/RS-485 links without external muxes. Speed grade -3 supports the 50-100 kHz switching loops typical of field-oriented control (FOC) algorithms, while the SRAM configuration cell enables firmware upgrades in the field as new motor-tuning parameters ship. The 220 C peak-reflow tolerance and MSL 3 rating suit standard factory SMT lines. The APEX 20K's MultiCore architecture lets the EAB blocks implement encoder-capture lookup tables directly on-die.
Recommended
Legacy ASIC Prototyping and Emulation
ASIC prototyping and hardware emulation are classic applications for the EP20K400FI672-3X, where its 400K system gates accommodate mid-complexity ASIC RTL with about 70-80 percent utilization. The 502 user I/Os allow mapping of wide internal ASIC buses (32-64 bit) directly to prototype headers without external logic, and the 3.6 ns propagation delay approximates typical ASIC gate delays for accurate timing verification. Quartus II design flows include the APEX 20K library for HDL synthesis and incremental compile, letting teams re-target older ASIC code that was originally prototyped on APEX 20K before tape-out. The industrial temperature grade also allows prototype boards to ship to customer field trials without redesign.
Recommended
Military and Aerospace Avionics Upgrades
Long-life avionics and military electronics platforms use the EP20K400FI672-3X because the APEX 20K family is on controlled-procurement lists that have remained in production for 25+ years. The industrial/extended temperature grade ('X') and 502 I/O lines support legacy MIL-STD-1553, ARINC 429, and discrete avionics buses. The SRAM-based configuration cell is paired with radiation-mitigation techniques (watchdog config re-load, TMR on critical logic) for high-altitude platforms. Designers can re-spin older Altera FLEX 10K-based boards onto the APEX 20K without a full PCB redesign because the BGA packages share similar footprints and JTAG toolchains.
Recommended
Medical Imaging Front-End Processing
Ultrasound and patient-monitoring front-ends use the EP20K400FI672-3X for high-channel-count analog-front-end aggregation. The 502 I/O lines accept 64-128 channel ADC data streams at 30-65 MHz, and the EAB (Embedded Array Block) memory implements line buffers and FIR filters directly on-die, eliminating external SRAM in cost-sensitive designs. Speed grade -3 sustains the ~80 MHz sample rate typical of mid-range ultrasound beamformers, and the 2.5 V core keeps power dissipation manageable in fan-less enclosures. The APEX 20K's deterministic timing supports IEC 60601-1 compliant designs where latency must be predictable for safety-critical signal chains.
Recommended
Test and Measurement Instrumentation
Digital test instruments such as logic analyzers, protocol testers, and bit-error-rate testers use the EP20K400FI672-3X to capture and pattern-generate wide parallel buses. The 502 I/O count and 833 MHz internal clock allow 32-bit @ 200 MHz pattern generation or 64-bit @ 100 MHz capture without external muxing, and the 3.6 ns propagation delay supports sub-ns edge placement in timing-critical test sequences. The industrial temperature grade ensures bench-top instruments operating in non-climate-controlled labs continue to function. JTAG-based configuration lets test engineers hot-swap personality bitstreams between product test patterns.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-3X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FI672-3V | EP20K400FI672-3N | EP20K400FI672-3 | EP20K400FI672-2X | EP20K400FI672-1X | EP20K400EFI672-2X |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-BGA (S-PBGA-B672, 1.0 mm pitch) | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same | 672-BGA (S-PBGA-B672, 1.0 mm pitch) - same |
| System Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 |
| Speed Grade | -3 | -3 | -3 | -3 | -2 | -1 | -2 |
| Temperature Grade | Industrial / Extended (X) | Commercial (V) | Industrial (N) | Commercial | Industrial / Extended (X) | Industrial / Extended (X) | Industrial / Extended (X) |
| Maximum User I/O | 502 | 502 | 502 | 502 | 502 | 502 | 502 |
| Core Voltage (VCCINT) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) | 2.5 V (2.375-2.625 V) |
| Silicon Revision | Original APEX 20K | Original APEX 20K | Original APEX 20K | Original APEX 20K | Original APEX 20K | Original APEX 20K | Enhanced ('E') APEX 20K |
Key Differentiators
- Highest I/O count in the APEX 20K family at 502 user I/O (vs EP20K400FI672-3V)
- Industrial/extended temperature grade ('X' suffix) (vs EP20K400FI672-3)
- Speed grade -3 silicon for maximum fMAX within 672-BGA family (vs EP20K400FI672-2X)
Design Notes
Decouple each VCCINT pin with a 0.1 uF X7R ceramic within 5 mm of the ball, plus one bulk 10-22 uF tantalum or polymer cap per VCCINT island. VCCIO banks should each have their own 0.1 uF plus bulk capacitor because mixed-voltage I/O standards (LVCMOS33, LVCMOS25, LVTTL) draw transient current during simultaneous switching. Estimated: with 400K gates switching at 100 MHz, dynamic current per VCCINT island can reach 200-300 mA - size the bulk caps to hold VCC ripple under 50 mV peak.
The 672-ball BGA at 1.000 mm pitch requires via-in-pad (VIP) or dog-bone fan-out routing on a minimum 6-layer stack-up. Use 0.2 mm laser-drilled microvias for inner-row escape, and avoid serpentine trace tuning on clock traces longer than 25 mm - use length-matched differential pairs with 100 ohm impedance. Thermal vias under the die (0.3 mm pitch grid) are required because the FG/FI BGA does not have an integrated thermal lid - solder a copper coin or heat-spreader for >2 W dissipation scenarios.
Do not confuse the EP20K400FI672 (fine-pitch BGA) with the EP20K400BC652 or EP20K400CB652 (different 652-ball package) - the ball maps are NOT compatible and a PCB designed for one will not accept the other. Also confirm the MSL 3 rating is respected: bake the parts for 48 hours at 125 C before assembly if the sealed pack has been open longer than the floor-life specified on the moisture-barrier bag.
Keep JTAG TCK, TMS, TDI, TDO traces short (<50 mm) and length-matched within 25 mm to avoid scan-chain timing violations. Provide a robust external configuration PROM (EPC2LC20 or EPC16) because the SRAM configuration cell is volatile - any power glitch longer than ~50 us will corrupt the bitstream and require a CONF_DONE-driven reconfiguration. Add a hardware watchdog that pulses nCONFIG if CONF_DONE stays low longer than 100 ms after nCONFIG goes high.
Compliance Information
RoHS compliance per Intel/Altera product page. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC. Conflict-minerals declaration filed per Section 1502 of the Dodd-Frank Act.
