EP20K600CF672C7 - 600K Gates APEX-20KC FPGA, 672-FBGA | Intel
MPN: EP20K600CF672C7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2362.39 | $2,362.39 |
| 10 | $2340.05 | $23,400.50 |
| 100 | $2315.14 | $231,514.00 |
| 500 | $2291.52 | $1,145,760.00 |
| 1,000 | $2267.89 | $2,267,890.00 |
EP20K600CF672C7 Overview
A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable routing, and I/O cells that engineers can reconfigure post-manufacturing to implement arbitrary digital logic. FPGAs sit within the broader taxonomy of programmable logic devices (PLDs) -> logic ICs -> integrated circuits, and they typically outperform discrete logic on density, speed, and design iteration cost while trading off absolute performance per gate against an ASIC. APEX-20KC devices in particular add dedicated CAM (Content-Addressable Memory) blocks alongside the LUT-based logic fabric, which historically made them attractive for networking forwarding tables and pattern matching.
Key specifications of the EP20K600CF672C7 include 508 user I/O pins, a propagation delay figure of approximately 1.48 ns in the digchip-published datasheet summary, an operating temperature range of 0C to 85C, and 1.27 mm BGA pitch on a 27 mm x 27 mm substrate. The 'C7' speed grade denotes the slowest commercial tier of the family, while the 'CF' package suffix identifies the 672-ball Fine-pitch Ball Grid Array.
The architecture combines four types of building blocks - MegaLAB structures, Logic Array Blocks (LABs), Embedded System Blocks (ESBs) for CAM/dual-port RAM, and a fast interconnect network - giving designers 24 macrocell-equivalent cells per LAB with high-speed row/column routing. With 24,320 cells distributed across the die, the device targets medium-to-large logic consolidation designs where several discrete CPLDs and glue logic would otherwise be required.
Typical applications for the EP20K600CF672C7 include telecom line-card interfaces, industrial control and instrumentation front-ends, PCI/PCI-X bus bridges, network switch fabric glue logic, and high-speed data-acquisition pre-processors. The 672-ball FC-FBGA package is designed for surface-mount assembly on multi-layer PCBs with controlled-impedance traces for LVDS, SSTL, and LVTTL I/O standards.
Designers should note that the APEX-20KC family has reached end-of-life status; new designs should target Cyclone, Arria, or Stratix equivalents. When working with legacy stock, validate that the 1.8V core supply rails are properly decoupled with low-ESR ceramic capacitors placed within 5 mm of the VCCINT balls, and that the JTAG chain is properly terminated per IEEE 1149.1.
This page synthesizes distributor pricing, parametric specifications, drop-in same-family alternatives from the APEX-20K series, and practical design notes not consolidated in a single manufacturer datasheet.
Drop-in alternatives for EP20K600CF672C7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672C7 (same form factor and footprint) — differing in Process Technology, Speed Grade, Package, Family, Device Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C6
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$480 / Unit
View Datasheet →EP20K600CF672C-7
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1620 / Unit
View Datasheet →EP20K600CF672C-8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1150 / Unit
View Datasheet →EP20K600CF672C-9
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$171 / Unit
View Datasheet →EP20K600CB672C7
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$182.5 / Unit
View Datasheet →EP20K600CF33C7
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$105.4 / Unit
View Datasheet →EP20K600CF672C7 Maximum Ratings & Electrical Characteristics
| Family | APEX-20KC |
| Device Type | SPLD / FPGA |
| System Gates | 600,000 |
| Logic Cells | 24,320 |
| User I/O | 508 |
| Package | 672-ball FC-FBGA (27x27 mm) |
| Ball Pitch | 1.27 mm |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V |
| Process Technology | 0.15 um CMOS, all-layer copper |
| Propagation Delay (typ.) | 1.48 ns |
| Operating Temperature | 0C to 85C (commercial) |
| Speed Grade | C7 |
| Embedded Memory | Dual-port RAM via ESBs |
| CAM Support | Yes (ESB-based content-addressable memory) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
EP20K600CF672C7 672-ball fc-fbga (27x27 mm) Pin Configuration Guide
Pin configuration for EP20K600CF672C7 (672-ball fc-fbga (27x27 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672C7.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672C7 is suitable for 7 applications: Telecom Line-Card Interface, PCI/PCI-X Bus Bridge, Network Switch Fabric Glue Logic, Industrial Control Front-End, High-Speed Data Acquisition Pre-Processor, ASIC Prototyping and Logic Consolidation, Legacy Avionics and Defense Display Controllers.
Telecom Line-Card Interface
The EP20K600CF672C7's 508 user I/Os and 24,320 logic cells give it the bandwidth needed for legacy telecom line-card glue logic, including TDM bus aggregation and HDLC framing. The 1.8 V core and 3.3 V VCCIO support LVTTL/LVCMOS interfaces common to T1/E1 framers, while the ESB-based dual-port RAM blocks eliminate external FIFOs for elastic buffering. Per the APEX-20K datasheet, the C7 speed grade comfortably meets 77 MHz synchronous timing budgets typical of older telecom backplanes.
Recommended
PCI/PCI-X Bus Bridge
With 508 I/Os, the EP20K600CF672C7 can implement a 64-bit, 66 MHz PCI-X bridge plus target logic on a single device, replacing two-to-three discrete CPLDs. The C7 speed grade meets PCI-X 66 MHz setup/hold margins per the APEX-20K family datasheet, and the ESB blocks provide the parity/check RAM needed for bus parity generation. Designers should instantiate the altpcix_mt32 mega-function from Quartus II to reuse verified PCI-X IP.
Recommended
Network Switch Fabric Glue Logic
The APEX-20KC's ESB-based Content-Addressable Memory blocks make the EP20K600CF672C7 particularly attractive for Layer-2/Layer-3 forwarding tables and MAC-address lookup engines. With 24,320 logic cells plus dedicated CAM, a single device can implement a 16K-entry IPv4 forwarding table with priority encoders and TCAM-shadow RAM. Per the APEX-20KC datasheet, CAM access times are competitive with discrete TCAM chips for line-rate gigabit forwarding.
Recommended
Industrial Control Front-End
The 0C to 85C commercial temperature range, robust 672-ball FC-FBGA package, and 508 I/Os make the EP20K600CF672C7 a fit for industrial PLC and motion-control front-ends where many discrete sensors and actuators must be aggregated. The 1.8 V core and 3.3 V I/O coexist with industrial 24 V signal-conditioning front-ends via external level shifters. The C7 speed grade comfortably handles 40 MHz encoder counter loops typical of servo drives.
Recommended
High-Speed Data Acquisition Pre-Processor
The 24,320 logic cells and ESB-based dual-port RAM let the EP20K600CF672C7 serve as a real-time pre-processor between ADCs and a host DSP/FPGA. With 508 I/Os, the device can source-synchronous-capture multiple LVDS data streams at up to 622 Mbps per the APEX-20K I/O specification, then buffer them into ESB RAM before DMA to the host. The C7 speed grade supports 200 MHz internal operation, sufficient for 16-channel 14-bit ADC aggregation.
Recommended
ASIC Prototyping and Logic Consolidation
Engineers used the EP20K600CF672C7 to consolidate multiple discrete 74-series and PAL/GAL devices onto a single programmable part during the early-2000s ASIC prototyping era. With 600K system gates and 508 I/Os, a single APEX-20KC could replace 8-10 discrete logic packages, shrinking PCB area and BOM cost. The C7 speed grade, while slower than C9, is sufficient for the <100 MHz control logic typical of these consolidation designs.
Recommended
Legacy Avionics and Defense Display Controllers
The EP20K600CF672C7's 508 I/Os and ESB dual-port RAM make it suitable for legacy military and avionics display controllers, where multi-standard video timing generation and overlay composition are required. Per the APEX-20K datasheet, the device supports LVDS, LVPECL, and 3.3 V PCML I/O standards via dedicated True-LVDS circuitry, enabling direct interface to flat-panel display drivers without external serializer ICs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672C7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C6 | EP20K600CF672C-7 | EP20K600CF672C-8 | EP20K600CF672C-9 | EP20K600CB672C7 |
|---|---|---|---|---|---|---|
| Package | 672-FBGA (27x27) | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA - same footprint, smaller die |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| System Gates | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 | 400,000 |
| Logic Cells | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 | 16,160 |
| User I/O | 508 | 508 | 508 | 508 | 508 | 488 |
| Speed Grade | C7 | C6 (faster) | C7 (same) | C8 (faster) | C9 (fastest) | C7 (same) |
| Core Voltage | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V |
| Operating Temperature | 0C to 85C | 0C to 85C | 0C to 85C | 0C to 85C | 0C to 85C | 0C to 85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 600K system gates with 508 user I/Os (vs EP20K400CF672C7)
- ESB-based dual-port RAM and CAM blocks (vs Discrete TCAM + SRAM chips)
- Speed grade flexibility within same package (vs EP20K600CF672C9 (C9 grade))
- Multi-standard I/O support (vs Cyclone IV (newer family))
Design Notes
The EP20K600CF672C7 requires a tightly regulated 1.8 V VCCINT rail with tolerance +/-5%. Estimated: at 200 MHz internal operation with 60% toggle rate across all 24,320 logic cells, core current can reach 1.5 A. Place four 10 uF X5R ceramic capacitors and twelve 0.1 uF decoupling capacitors around the package perimeter, within 5 mm of the VCCINT balls. The VCCIO banks (3.3 V typical) should be decoupled similarly with 22 uF bulk + 0.1 uF per pin group.
At full utilization (24,320 cells at 200 MHz, 60% toggle), the EP20K600CF672C7 dissipates an estimated 2.7 W. The 672-FBGA package has a theta_JA of approximately 18 C/W with a standard 4-layer JEDEC test board, giving a 49 C junction rise above ambient - well within the 0C-85C commercial range. For high-altitude or enclosed applications, attach a heatsink or use thermal vias under the package center array to maintain the 125 C junction limit.
The 1.27 mm ball pitch on the 672-FBGA package requires 0.6 mm pad diameter and 0.4 mm solder-mask openings per IPC-7351. Use a 4-layer stack-up with continuous GND planes on layers 2 and 4, and route LVDS pairs with 100 ohm differential impedance. Keep all 16 GND balls connected directly to the inner GND plane with stitched vias; never daisy-chain GND returns on a BGA.
Common pitfalls when designing with the EP20K600CF672C7: (1) confusing the C7 speed grade with the I7 industrial-temperature variant - the latter has -40C to +100C support and a different ordering code; (2) failing to level-shift between 3.3 V VCCIO and 5 V peripherals - the APEX-20K I/O is NOT 5 V tolerant; (3) using the older MAX+PLUS II toolchain instead of Quartus II, which does not support APEX-20KC CAM blocks.
Source-synchronous LVDS interfaces on the EP20K600CF672C7 should use the dedicated True-LVDS circuitry with 100 ohm differential termination at the receiver end. Estimated: at 622 Mbps, intra-pair skew must be held below 50 ps to maintain the LVDS eye mask; this requires matched-length routing on the PCB with 5 mil tolerance per Altera AN-224 (SignalTap II margin measurement). Use series AC-coupling capacitors on receive pairs when interfacing to AC-coupled transceivers.
Compliance Information
RoHS and REACH compliance confirmed via the Altera/Intel material declaration; AEC-Q100 is not applicable as this is a commercial-grade FPGA not qualified for automotive use. The part is no longer in active production.
