Intel

EP20K600CB672C8N - APEX-20KC FPGA 24K LE 672-BGA | Intel

MPN: EP20K600CB672C8N ✗ End of Life

In Stock Ships in 1-3 business days

2.5 V Vdss 672-BBGA (FineLine BGA) Package C8 Speed 311,296 Memory

From $69 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$95	$95.00
10	$88.5	$885.00
100	$82	$8,200.00
500	$75.5	$37,750.00
1,000	$69	$69,000.00

ℹ️ All prices are in USD

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EP20K600CB672C8N Overview

The Intel (formerly Altera) EP20K600CB672C8N is an APEX-20KC family Field-Programmable Gate Array (FPGA) with 24,320 logic elements, 311,296 bits of embedded memory and 508 maximum user I/O pins, housed in a 672-ball FineLine BGA (BBGA) package. It is fabricated on a 0.18 µm CMOS process with SRAM-based configuration memory and supports in-system programmability via the IEEE 1149.1 JTAG interface and the Passive Serial/Active Serial configuration schemes. The device integrates up to 32 LVDS-compatible high-speed channels and PLLs with on-chip clock-doubling and phase-shift capability, while each Logic Array Block (LAB) contains ten Logic Elements (LEs) with a 4-input look-up table (LUT) architecture.

An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks, embedded memory, routing interconnect and I/O cells that the designer programs after manufacture. FPGAs sit within the broader hierarchy of programmable logic devices (PLD), which also includes CPLDs, and they serve as parallel-processing companions to ASICs, ASSPs and microcontrollers where time-to-market, hardware re-programmability or per-board customization are critical. APEX-20KC parts are considered high-density members of the APEX-20K family, designed for datapath-intensive designs that combine wide datapaths, on-chip memory and high I/O counts.

Key features include MultiVolt I/O support (1.8 V, 2.5 V and 3.3 V interfaces with a 2.5 V core), PCI-SIG compliant 3.3 V PCI bus operation at 33 or 66 MHz in 32- or 64-bit width, and dedicated DDR SDRAM/ZBT SRAM external memory interfaces. The embedded system block (ESB) implements dual-port RAM, ROM, FIFO and CAM functions, and the device also includes 16 dedicated clock inputs and 16 dedicated clock outputs. Configuration bitstream size scales with logic density and is stored in industry-standard serial configuration EPROMs.

Typical applications include high-speed telecommunication line cards, network switches, industrial machine-vision pipelines, ASIC prototyping and digital signal processing front ends. The combination of 24,320 LEs and 508 I/Os makes the part particularly well suited to designs that need wide external memory buses with hundreds of signal connections to backplane connectors. Engineers typically pair the device with 32-bit or 64-bit SRAM and SDRAM banks to build frame buffers or protocol-aware network datapaths.

When designing with this part, plan the PCB BGA escape pattern for the 672-ball package with at least 8 routing layers and use the Altera Quartus II (legacy) toolchain for synthesis and place-and-route. Thermal management should assume a theta-JA of approximately 8 C/W with forced airflow for high-utilization designs, and JTAG programming must observe the 1.8/2.5/3.3 V VCCIO ramp sequencing noted in the APEX-20KC datasheet.

Drop-in alternatives for EP20K600CB672C8N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K600CB672C8N (same form factor and footprint) — differing in Process Technology, Operating Temperature, Speed Grade, Family, Device Type.

EP20K600CB672C7

Altera

Process Technology: 0.15 µm all-layer copper-metal CMOS

Operating Temperature: 0 °C to 85 °C (commercial)

Speed Grade: C7 (commercial, 0 °C to 85 °C)