EP2A70F1020C9 - APEX II 70K FPGA, 735 I/O, 1020-BGA | Intel
MPN: EP2A70F1020C9 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $215.5 | $2,155.00 |
| 100 | $178 | $17,800.00 |
| 500 | $152.4 | $76,200.00 |
| 1,000 | $132.8 | $132,800.00 |
EP2A70F1020C9 Overview
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) that belongs to the broader semiconductor and integrated circuit hierarchy. FPGAs contain configurable logic blocks (CLBs), programmable interconnect, and dedicated I/O resources that engineers can reconfigure post-manufacturing to implement custom digital circuits, processors, or signal-processing pipelines. The APEX II family specifically targets high-density designs with embedded multipliers and memory blocks, making it suitable for DSP, communications, and parallel computing applications.
Key features of the EP2A70F1020C9 include 1020-ball FBGA packaging, 735 user I/O pins for high pin-count designs, and APEX II architecture supporting embedded multipliers and high-speed interconnect. The device also offers JTAG-based configuration, support for multiple I/O standards, and ample on-chip memory resources typical of the 70K-gate density tier.
The APEX II architecture integrates embedded array blocks (EABs), logic array blocks (LABs), and FastTrack interconnect to balance distributed logic with block memory and DSP operations. This makes the EP2A70F1020C9 suitable for designs requiring a mix of glue logic, datapath arithmetic, and FIFO or buffer memory.
Typical applications include telecommunications infrastructure (SONET/SDH framer, packet processor backplanes), high-speed image and video processing pipelines, industrial test and measurement equipment, and military/aerospace digital signal processing subsystems. Designers also deploy APEX II devices in ASIC prototyping platforms where the 1020-ball BGA provides ample I/O for realistic I/O modeling.
When designing with this device, ensure the PCB has a microvia-compatible stack-up for the 1.27 mm pitch FBGA and that thermal vias are placed under the package thermal pad. Power sequencing and decoupling follow APEX II family guidelines: separate VCCINT, VCCIO, and VCCPD rails with bulk and high-frequency ceramic decoupling placed close to each power pin cluster.
Drop-in alternatives for EP2A70F1020C9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2A70F1020C9 (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, Speed Grade, System Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2A70F1020C8
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View Datasheet →EP2A70F1020C7
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View Datasheet →EP2A40F1020C9
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View Datasheet →EP2A40F1020C8
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View Datasheet →EP2A40F1020C7
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View Datasheet →EP2A70F1020C9 Maximum Ratings & Electrical Characteristics
| Family | APEX II (APII) |
| Manufacturer | Intel (formerly Altera) |
| Typical Gates | ~70,000 gates |
| Package | 1020-ball FBGA (FineLine BGA) |
| User I/O Pins | 735 |
| Speed Grade | -9 (fastest) |
| Operating Temperature Grade | Commercial (C) |
| Configuration Method | JTAG / passive serial / passive parallel |
| On-chip Memory | EABs (Embedded Array Blocks) |
| Embedded Multipliers | Yes (DSP blocks in LABs) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (JEDEC J-STD-020) |
EP2A70F1020C9 1020-ball fbga (fineline bga) Pin Configuration Guide
Pin configuration for EP2A70F1020C9 (1020-ball fbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2A70F1020C9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2A70F1020C9 is suitable for 6 applications: Telecommunications Infrastructure, High-Speed Image and Video Processing, Industrial Test and Measurement Equipment, ASIC Prototyping Platforms, Military and Aerospace Digital Signal Processing, High-Performance Parallel Computing.
Telecommunications Infrastructure
The EP2A70F1020C9 fits telecommunications infrastructure designs such as SONET/SDH framers, packet-processor backplanes, and ATM switch fabric interfaces. The 735 user I/O pins provide enough headroom for parallel UTOPIA, POS-PHY, or proprietary interconnect buses, while the ~70K-gate density accommodates channelizers, scramblers, and cell-processing pipelines. APEX II EABs deliver high-throughput FIFO and CAM-style lookups needed in switching fabrics. Designers typically place the FPGA between a network processor and SERDES transceivers, using the device for protocol encapsulation and traffic management.
Recommended
High-Speed Image and Video Processing
The EP2A70F1020C9 serves well in high-speed image and video processing pipelines such as real-time video mixers, multi-channel video capture cards, and image pre-processing front ends for medical imaging or machine vision. Its 735 I/O pins accommodate wide parallel pixel buses (up to 64-bit wide at common pixel clocks), while the embedded multipliers in APEX II LABs enable convolution and filtering operations in hardware. EABs implement line buffers and lookup tables required for color-space conversion and gamma correction. Typical placement is between image sensor FIFOs and a host processor.
Recommended
Industrial Test and Measurement Equipment
The EP2A70F1020C9 supports industrial test and measurement equipment such as logic analyzers, protocol exercisers, automated test equipment (ATE) pin electronics, and high-channel-count data-acquisition backplanes. APEX II EABs implement pattern generators and capture buffers, while the wide I/O count lets a single FPGA drive dozens of test channels with per-pin timing alignment. Designers rely on the device for mixed-signal test sequencing and parallel stimulus/response handling.
Recommended
ASIC Prototyping Platforms
The EP2A70F1020C9 is used in ASIC prototyping platforms where the 1020-ball FBGA exposes enough user I/O to map real ASIC pad signals one-to-one for accurate I/O modeling. APEX II embedded array blocks (EABs) emulate ASIC SRAMs, and the device's large interconnect fabric simplifies partitioning large ASIC RTL into multi-FPGA prototypes. Design teams can map a sub-section of a large ASIC onto the ~70K-gate capacity of this part.
Recommended
Military and Aerospace Digital Signal Processing
The EP2A70F1020C9 has been used in legacy military and aerospace digital signal processing subsystems such as radar pre-processors, electronic-warfare channelizers, and secure-communication modem cards. The 735 I/O pin count supports parallel ADC/DAC interfaces in radar and EW systems, while APEX II embedded multipliers accelerate FFT and pulse-Doppler processing. Although the part is now obsolete, mature designs still benefit from its documented reliability and the existence of long-term-support channels.
Recommended
High-Performance Parallel Computing
The EP2A70F1020C9 fits high-performance parallel computing accelerator cards where the device implements custom SIMD datapaths, scatter-gather DMA engines, or co-processing pipelines alongside a host CPU. APEX II LABs with embedded multipliers provide the DSP throughput needed for scientific computing, and the 735 I/O pins expose wide memory buses to external SRAM or DDR banks. Placed between the host processor and memory, the FPGA offloads compute-intensive kernels such as matrix multiplication and signal transforms.
Recommended
Recommended Products Summary
Engineering reference data for EP2A70F1020C9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2A70F1020C8 | EP2A70F1020C7 | EP2A40F1020C9 | EP2A40F1020C8 | EP2A40F1020C7 |
|---|---|---|---|---|---|---|
| Package | 1020-ball FBGA | 1020-ball FBGA - same | 1020-ball FBGA - same | 1020-ball FBGA - same | 1020-ball FBGA - same | 1020-ball FBGA - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | APEX II | APEX II | APEX II | APEX II | APEX II | APEX II |
| Typical Gates | ~70,000 | ~70,000 | ~70,000 | ~40,000 (-43%) | ~40,000 (-43%) | ~40,000 (-43%) |
| Speed Grade | -9 | -8 | -7 | -9 | -8 | -7 |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Commercial | Commercial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Pin-to-Pin Compatible | Yes | Yes | Yes | Yes (different die) | Yes (different die) | Yes (different die) |
Key Differentiators
- Fastest speed grade in the 70K APEX II family (vs EP2A70F1020C8)
- Higher logic density than the EP2A40 family (vs EP2A40F1020C9)
- Larger user I/O than EP2A40 family in same package (vs EP2A40F1020C9)
Design Notes
The 1020-ball FineLine BGA uses a 1.27 mm ball pitch and typically requires a microvia-compatible PCB stack-up (e.g., 6+ layers with laser-drilled microvias). Use a high-Tg (>=170C) FR-4 or polyimide substrate. Fan-out routing must respect the APEX II ball map - the Xilinx-style staggered pattern is not used here. Place thermal vias in a grid pattern directly under the package thermal balls to keep junction temperature within spec.
APEX II devices require at least three separate power rails: VCCINT (core), VCCIO (I/O banks, multiple voltages allowed per bank), and VCCPD or auxiliary configuration supply. Decoupling must include bulk tantalum or polymer capacitors plus 0.1 uF and 0.01 uF ceramics placed within 100 mils of each power pin cluster. Power-up sequencing follows Intel's APEX II datasheet: drive CONFIG_DONE low until all rails are stable, and use a supervisor to hold the FPGA in reset if any rail dips out of spec.
With 735 user I/O pins running at high toggle rates, simultaneous switching output (SSO) noise is a real concern on the 1020-ball FBGA. Spread high-speed outputs across I/O banks, assign slower signals adjacent to sensitive analog or reference inputs, and add a generous VCCIO/GND via field. Use IBIS simulation (Altera/Intel provides APEX II IBIS models) to verify SSO margin before committing layout.
Do not assume the EP2A40F1020C* family is a logic-compatible substitute for EP2A70F1020C* - the die is smaller and any RTL that targets the 70K device may not fit in 40K gates. Always recompile through Quartus II or the APEX II design toolchain after substitution. Also, the part is obsolete: design teams should perform a lifetime buy analysis and validate second-source supply before committing to new production.
Compliance Information
Compliance fields marked unknown because the verified web data does not specify RoHS/REACH or lead-free status for the EP2A70F1020C9. The APEX II family pre-dates current Intel/Altera compliance documentation conventions. AEC-Q100 is not applicable because this is a commercial-grade FPGA, not an automotive-qualified part.
