EP2AGZ350FF35C3G - Arria II GZ FPGA 350K LE | Intel | 1152-FBGA
MPN: EP2AGZ350FF35C3G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3650 | $36,500.00 |
| 100 | $3275 | $327,500.00 |
| 500 | $2950 | $1,475,000.00 |
| 1,000 | $2680 | $2,680,000.00 |
EP2AGZ350FF35C3G Overview
An FPGA (Field-Programmable Gate Array) is a class of programmable logic device whose architecture consists of configurable logic blocks (CLBs), programmable routing, dedicated DSP blocks, on-chip memory, and (in transceiver families) hardened serial interface IP. Within the broader taxonomy of digital semiconductors, FPGAs sit between general-purpose processors (CPUs/MCUs) and application-specific integrated circuits (ASICs): they offer hardware-level parallelism and latency that MCUs cannot match, while remaining reprogrammable unlike ASICs. Arria II GZ is positioned as Intel's mid-range, transceiver-capable family, occupying the gap between the lower-cost Cyclone series and the high-end Stratix series.
Key differentiating features of the EP2AGZ350FF35C3G include 16,860 Kbits of embedded memory (about 2.1 MB), 224 dedicated 18x18 multipliers (or equivalent 9.4 GMACS DSP throughput), eight 6.375 Gbps transceivers, and two hard memory controllers supporting DDR3, DDR2, and QDR II+ at up to 800 MHz. Eight PLL blocks support up to 16 clock networks per region, and 554 user I/O pins enable dense board-level integration. The device operates from a 0.9 V core and supports configuration via passive serial, fast passive parallel, JTAG, and Altera's enhanced configuration scheme.
Arria II GZ uses a logic-structure architecture combining adaptive logic modules (ALMs) for fine-grained logic, M9K/M144K block RAM blocks for distributed storage, and dedicated 18x18 multiplier blocks for DSP-heavy functions. The transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) are hardened, simplifying serializer/deserializer (SERDES) integration for protocols such as PCIe Gen1/Gen2, XAUI, CEI-6G, CPRI, and Serial RapidIO.
Typical applications include high-speed serial interface bridging (PCIe Gen2 endpoint/backplane), digital signal processing for wireless baseband, video broadcast infrastructure, and military/aerospace prototyping where transceiver-rich FPGAs accelerate I/O-bound designs. Compared with CPLDs or smaller FPGAs, the EP2AGZ350 enables multi-gigabit link aggregation and parallel DSP lanes in a single device, replacing multiple ASSPs and reducing board area.
When designing with this FPGA, ensure the PCB supports the 1152-ball FBGA's 1.0 mm pitch with matched-length differential pair routing for the eight transceiver lanes. Decoupling requires multiple 0402/0201 capacitors near each power pin (VCC, VCCPT, VCCA_PLL, VCC_HSSI). Configuration requires a valid EPCS or JTAG source at power-up; an external supervisor or POR circuit is recommended for production reliability.
This page synthesizes distributor pricing, drop-in alternatives in the same 1152-FBGA footprint, and design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2AGZ350FF35C3G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FF35C3G (same form factor and footprint) — differing in Package, Transceivers, Speed Grade, RoHS Status, Logic Elements (LE).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGZ300FF35C3G
✅ Drop-In✓ In Stock
$1395 / Unit
View Datasheet →EP2AGZ225FF35C3G
✅ Drop-In✓ In Stock
$868.4 / Unit
View Datasheet →EP2AGZ350FF35C4G
✅ Drop-In✓ In Stock
$1395 / Unit
View Datasheet →EP2AGZ350FF35C6G
✅ Drop-In📋 Reference alternative (not in catalog)
EP2AGZ300FF35I3G
✅ Drop-In✓ In Stock
$1230 / Unit
View Datasheet →EP2AGZ350FF35C3G Maximum Ratings & Electrical Characteristics
| Family | Arria II GZ |
| Logic Elements (LE) | 350,000 |
| Embedded Memory | 16,860 Kbits |
| DSP Blocks (18x18 Multipliers) | 224 |
| Transceivers | 8 |
| Transceiver Data Rate | up to 6.375 Gbps |
| User I/O Pins | 554 |
| PLLs | 8 |
| Hard Memory Controllers | 2 |
| Memory Interface Support | DDR3, DDR2, QDR II+, RLDRAM II |
| Maximum Memory Clock | 800 MHz |
| Process Node | 40 nm TSMC |
| Package | 1152-FBGA (35 mm x 35 mm, 1.0 mm pitch) |
| Operating Temperature | 0C to +85C (commercial) |
| Core Voltage | 0.9 V |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG, AS |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (BGA) |
EP2AGZ350FF35C3G 1152-fbga (35 mm x 35 mm, 1.0 mm pitch) Pin Configuration Guide
Pin configuration for EP2AGZ350FF35C3G (1152-fbga (35 mm x 35 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FF35C3G.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FF35C3G is suitable for 6 applications: PCIe Gen2 Endpoint / Backplane Card, Wireless Baseband Signal Processing, Video Broadcast and Image Processing, 10G Ethernet Switching and Aggregation, Industrial Test and Measurement Instrumentation, Military / Aerospace Prototyping.
PCIe Gen2 Endpoint / Backplane Card
The EP2AGZ350FF35C3G is well suited to PCIe Gen2 endpoint and backplane designs because its eight hardened 6.375 Gbps transceivers directly support x1/x4 PCIe Gen1 (2.5 Gbps) and Gen2 (5.0 Gbps) operation without an external PHY. According to the Arria II GZ handbook, the hardened PCIe IP block delivers up to 256-byte payload, MSI/MSI-X interrupts, and up to four lanes per quad. The 350K LEs provide ample headroom for protocol state machines, DMA engines, and user application logic. With 554 user I/O pins exposed via the FF35 1152-FBGA, designers can route PCIe plus auxiliary control/status signals without muxing. Compared with adding discrete PCIe bridge chips, integrating the protocol in this FPGA reduces board area, BOM cost, and latency.
Recommended
Wireless Baseband Signal Processing
The EP2AGZ350FF35C3G fits wireless baseband signal processing because its 224 dedicated 18x18 multipliers deliver up to 9.4 GMACS, sufficient for multi-antenna MIMO equalization, FFT/iFFT pipelines, and channel coding at LTE-class sample rates. The 16,860 Kbits of block RAM lets designers build overlap-save FFT buffers, scrambling tables, and HARQ retransmission queues on-chip, eliminating external memory accesses on hot paths. Eight transceivers enable front-haul CPRI/OBSAI links to RFICs at up to 6.375 Gbps per lane, so the FPGA bridges baseband DSP and remote radio heads in a single device. With 554 user I/O and the FF35 BGA, the part supports JESD204B-style parallel RF data alongside control and synchronization signals.
Recommended
Video Broadcast and Image Processing
The EP2AGZ350FF35C3G accelerates video broadcast and image processing because its 350K logic elements support wide multi-tap filter trees, motion-estimation engines, and real-time color-space conversion pipelines running at full-HD or 4K resolutions. The 16,860 Kbits of embedded RAM serve as line buffers and frame stores, while the 224 multipliers accelerate 2D convolution, scaling, and deinterlacing kernels. The eight transceivers enable SDI, HDMI, and DisplayPort aggregation at multi-gigabit rates, making the device a single-chip ingest-and-process solution for broadcast routers. In the FF35 1152-FBGA package, 554 user I/O expose parallel video buses plus GPIO for control plane integration.
Recommended
10G Ethernet Switching and Aggregation
The EP2AGZ350FF35C3G is a strong fit for 10G Ethernet aggregation because its eight 6.375 Gbps transceivers align directly with SFP+/SFP cage interfaces and 10GBase-KR backplanes. The 350K LEs implement Layer 2/3 forwarding tables, ACL matching, and QoS shaping, while 16,860 Kbits of block RAM provide packet-header lookup caches and queue descriptors. The two hard memory controllers interface directly to DDR3 at up to 800 MHz, supporting large packet buffer pools without external TCAM. The FF35 1152-FBGA's 554 user I/O expose SPI/I2C management interfaces, LED drivers, and PTP timestamp signals alongside the high-speed serial lanes.
Recommended
Industrial Test and Measurement Instrumentation
The EP2AGZ350FF35C3G suits high-end T&M instruments because its parallel logic fabric plus 9.4 GMACS DSP throughput enable real-time FFT spectrum analysis, arbitrary waveform generation, and protocol decoding at multi-GSPS sample rates when paired with external ADCs. Eight transceivers support 10G/40G data offload to host processors without an additional NIC. The 16,860 Kbits of block RAM act as deep capture buffers, while 554 user I/O expose trigger, gate, and synchronization buses for bench and ATE rack integration. Industrial-temp drop-in alternatives like the EP2AGZ300FF35I3G allow the same PCB design to support harsh-environment deployment in factory automation cells.
Recommended
Military / Aerospace Prototyping
The EP2AGZ350FF35C3G is widely deployed in defense prototyping because its transceiver-rich fabric supports multi-protocol avionics buses (MIL-STD-1553, ARINC 429, SpaceWire) alongside encrypted links, all within one device. The 350K LEs enable cryptographic accelerators and signal-processing pipelines, while 16,860 Kbits of block RAM buffer sensor data prior to encryption or compression. The FF35 1152-FBGA exposes 554 user I/O for backplane integration with legacy MIL-1553 transceivers and modern high-speed serial links. Designers can switch to the EP2AGZ300FF35I3G industrial-temp variant for systems requiring -40C to +100C operation on the same pin-compatible footprint.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FF35C3G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ300FF35C3G | EP2AGZ225FF35C3G | EP2AGZ350FF35C4G | EP2AGZ350FF35C6G | EP2AGZ300FF35I3G |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | 1152-FBGA (FF35, 35x35 mm, 1.0 mm pitch) | 1152-FBGA (FF35) - same | 1152-FBGA (FF35) - same | 1152-FBGA (FF35) - same | 1152-FBGA (FF35) - same | 1152-FBGA (FF35) - same |
| Logic Elements | 350,000 | 300,000 (-14%) | 225,000 (-36%) | 350,000 (identical) | 350,000 (identical) | 300,000 (-14%) |
| Speed Grade | C3 (commercial, mid speed) | C3 - same | C3 - same | C4 (faster) | C6 (fastest) | I3 (industrial temp, same speed) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Transceivers | 8 channels at 6.375 Gbps | 8 at 6.375 Gbps - same | 8 at 6.375 Gbps - same | 8 at 6.375 Gbps - same | 8 at 6.375 Gbps - same | 8 at 6.375 Gbps - same |
| Embedded Memory | 16,860 Kbits | 14,290 Kbits (-15%) | 10,560 Kbits (-37%) | 16,860 Kbits (identical) | 16,860 Kbits (identical) | 14,290 Kbits (-15%) |
| DSP Blocks (18x18) | 224 multipliers | 192 (-14%) | 144 (-36%) | 224 (identical) | 224 (identical) | 192 (-14%) |
| User I/O | 554 | 554 (identical) | 554 (identical) | 554 (identical) | 554 (identical) | 554 (identical) |
Key Differentiators
- Highest logic density in the 1152-FBGA FF35 package at the C3 speed grade (vs EP2AGZ300FF35C3G)
- Mid-tier C3 speed grade balances timing margin and cost (vs EP2AGZ350FF35C6G)
- Commercial 0C to +85C operation supports lab and indoor deployments (vs EP2AGZ300FF35I3G)
Design Notes
The 1152-ball FF35 BGA uses 1.0 mm ball pitch on a 35 mm x 35 mm substrate. Use at least 8-layer PCB stackup with dedicated ground and power planes directly under the BGA. Via-in-pad with filled-and-capped microvias is recommended to escape inner-row balls; outer-row escape uses standard 8 mil drilled vias with 16 mil antipads. Matched-length (within 5 mil) differential pair routing is required for each of the eight transceiver lanes, with 100-ohm differential impedance and continuous reference planes on adjacent layers. AC coupling capacitors (100 nF 0402 X7R) must be placed within 0.5 inches of each transceiver TX/RX ball per the Arria II GZ handbook.
Estimated power: at 50% utilization with eight active transceivers and 800 MHz DDR3 controllers, expect 8-12 W of total power, supplied as VCC core (0.9 V), VCCPT, VCCA_PLL, VCC_HSSI, and VCCIO banks. Decoupling requires bulk 470 uF tantalum or polymer caps at the voltage regulator outputs plus 22 uF and 4.7 uF ceramics distributed across the BGA footprint. Place 0402 0.1 uF / 1 nF / 10 nF caps within 100 mil of every VCC and VCCIO pin; the PLL analog supply (VCCA_PLL) needs its own ferrite-filtered island to reduce jitter. A power-sequencer IC such as the LTC2974 is recommended to enforce core-before-I/O ramp order.
Common pitfalls when bringing up the EP2AGZ350FF35C3G include: (1) failing to initialize the configuration flash (EPCS) before first JTAG programming, (2) leaving CONFIG_DONE or nSTATUS floating rather than pulling up with 10 kohm, (3) ignoring MSEL pin strapping which selects AS/PS/JTAG configuration mode, and (4) routing single-ended clock inputs without considering the required 50-ohm termination. Always reset and re-program the configuration flash after any silicon revision update, and verify that all JTAG TCK/TMS/TDO/TDI lines are buffered if multiple devices share the JTAG chain.
Estimated junction-to-ambient thermal resistance (theta_JA) of the FF35 1152-FBGA is around 12 C/W with a 4-layer JEDEC test board, dropping to 8-9 C/W with a 12-layer board plus thermal vias under the central ball grid. At 10 W of internal dissipation this yields an 80-120 C temperature rise above ambient - within the commercial 0C to +85C spec at room temperature but potentially exceeding it in enclosed chassis. For deployment in dense PCIe card form factors, add a heatsink with thermal interface material plus forced airflow of 200 LFM minimum.
Compliance Information
RoHS compliant per Intel/Altera product page. Lead-free BGA balls per JEDEC J-STD-020. AEC-Q100 not applicable - FPGAs are not automotive-qualified semiconductors in this product line.
