EP2AGZ350FF35I3 - Arria II GZ 350K LE FPGA | Intel FPGA
MPN: EP2AGZ350FF35I3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5511.47 | $5,511.47 |
| 10 | $5226.5 | $52,265.00 |
| 25 | $4960.32 | $124,008.00 |
| 100 | $4684.95 | $468,495.00 |
| 500 | $4409.18 | $2,204,590.00 |
EP2AGZ350FF35I3 Overview
An FPGA (field-programmable gate array) is a class of programmable logic device whose function is determined by user-defined configuration rather than fixed silicon. Within the broader programmable logic taxonomy, FPGAs rank alongside CPLDs (complex programmable logic devices) under the umbrella of programmable logic, sitting above fixed-function ASICs only in flexibility and below microcontrollers in ease of programming. Arria II GZ devices were specifically optimized for transceivers, DSP blocks, and on-chip memory bandwidth, bridging the gap between Cyclone (cost-optimized) and Stratix (performance-optimized) families.
Key features of the EP2AGZ350FF35I3 include up to 16 transceivers operating at 6.375 Gbps, dedicated variable-precision DSP blocks totaling approximately 1,368 18x19 multipliers, 554 user I/O supporting LVDS, LVTTL, LVCMOS, HSTL, and SSTL standards, and an industrial operating range (-40C to +100C junction). On-chip PLLs support clock synthesis for multi-gigabit transceivers, memory interfaces including DDR3, and general-purpose system clocks. Hard memory controllers and PCIe Gen2 hard IP blocks reduce soft-logic footprint and improve timing closure.
Typical applications for this device include high-resolution broadcast video processing, wireless baseband aggregation, medical imaging pipelines, radar signal processing, and protocol bridging between PCIe, Serial RapidIO, and 10 Gigabit Ethernet. The industrial temperature grade also supports defense and aerospace subsystems where extended thermal range is mandatory. The combination of logic density and high-speed serial I/O makes the EP2AGZ350FF35I3 a flexible mid-tier platform for ASIC prototyping and pre-silicon validation.
When designing with this device, ensure your PCB BGA escape routing respects the 1.0 mm ball pitch and that the flip-chip thermal pad is properly soldered to a sufficient copper area. Use Altera Quartus II design software for synthesis, place-and-route, and timing analysis. Carefully review transceiver reference clock jitter, which directly limits the achievable Gbps rate.
Drop-in alternatives for EP2AGZ350FF35I3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2AGZ350FF35I3 (same form factor and footprint) — differing in Package, Transceivers, RoHS Status, Logic Elements, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2AGZ350FF35C3N
✅ Drop-In✓ In Stock
$2250 / Unit
View Datasheet →EP2AGZ350FF35C4N
✅ Drop-In✓ In Stock
$2150 / Unit
View Datasheet →EP2AGZ350FF35C3G
✅ Drop-In✓ In Stock
$2680 / Unit
View Datasheet →EP2AGZ350FF35C4G
✅ Drop-In✓ In Stock
$1395 / Unit
View Datasheet →EP2AGZ300FF35I3N
✅ Drop-In✓ In Stock
$3500 / Unit
View Datasheet →EP2AGZ300FF35I3G
✅ Drop-In✓ In Stock
$1230 / Unit
View Datasheet →EP2AGZ350FF35I3 Maximum Ratings & Electrical Characteristics
| Series | Arria II GZ |
| Logic Elements (LE) | 348,500 |
| Embedded Memory Bits | 21,270,528 bits |
| Maximum User I/O | 554 |
| Transceivers | Up to 16 channels |
| Transceiver Data Rate | 6.375 Gbps |
| Process Node | 40 nm |
| Package | 1152-ball FCBGA (FF35) |
| Ball Pitch | 1.0 mm |
| Operating Temperature Grade | Industrial (-40C to +100C Tj) |
| Configuration Method | FPGA configuration via Altera Quartus II |
| Hard IP Blocks | PCIe Gen2 hard IP, memory controllers, PLLs |
| RoHS Status | Compliant per distributor listings |
| MSL Level | 3 (per typical Altera FCBGA handling) |
EP2AGZ350FF35I3 1152-ball fcbga (ff35) Pin Configuration Guide
Pin configuration for EP2AGZ350FF35I3 (1152-ball fcbga (ff35) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2AGZ350FF35I3.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2AGZ350FF35I3 is suitable for 6 applications: High-Resolution Broadcast Video Processing, Wireless Baseband Aggregation, Medical Imaging Pipelines, Radar Signal Processing, ASIC Prototyping and Pre-Silicon Validation, Industrial Protocol Bridging.
High-Resolution Broadcast Video Processing
The EP2AGZ350FF35I3's 348,500 logic elements and 21,270,528 embedded memory bits provide the throughput needed for multi-stream 3G-SDI/HD-SDI video processing pipelines, where parallel pixel-domain manipulation across multiple channels demands sustained high logic utilization. The 16 transceivers at 6.375 Gbps aggregate enough bandwidth to handle uncompressed 1080p60 video streams and 4K upscaling at the input, while the dedicated variable-precision DSP blocks accelerate color-space conversion and chroma keying operations that would otherwise consume general logic. Industrial temperature grade (-40C to +100C Tj) suits outdoor broadcast trucks and studio environments.
Recommended
Wireless Baseband Aggregation
The EP2AGZ350FF35I3 is widely deployed in wireless baseband units where CPRI and OBSAI fronthaul links require multi-gigabit serial I/O at exactly the 6.375 Gbps tier the Arria II GZ transceivers deliver. The 554 user I/O pins aggregate enough baseband data lanes from multiple radio heads, while the dedicated DSP blocks perform channel filtering, FFT/iFFT, and crest-factor reduction without consuming general fabric. Hard PCIe Gen2 IP enables direct connection to a baseband processor, eliminating an external bridge chip and shrinking BOM cost.
Recommended
Medical Imaging Pipelines
Medical imaging systems such as ultrasound beamformers and MRI digitizers use the EP2AGZ350FF35I3 to process parallel data streams from transducer arrays with deterministic latency. The 348,500 logic elements and large embedded memory pool (21M bits) hold temporary image frames and FIR filter coefficients, while the DSP blocks perform real-time beamforming math with low fabric latency. Industrial temperature grade ensures stable operation in controlled clinical settings, and the FCBGA package supports the high pin density required for parallel LVDS sensor interfaces.
Recommended
Radar Signal Processing
The EP2AGZ350FF35I3 is well suited to phased-array radar preprocessing where multiple high-speed ADC sample streams must be buffered, windowed, and FFT-processed in real time. The device's 6.375 Gbps transceivers accept ADC data directly from JESD204B-compatible converters, while the variable-precision DSP blocks execute the FFT cores, pulse compression, and MTI filtering that radar algorithms demand. Memory bandwidth is sufficient to maintain range-Doppler maps without external DRAM access on every cycle.
Recommended
ASIC Prototyping and Pre-Silicon Validation
The EP2AGZ350FF35I3's combination of 348,500 logic elements, 21M bits of embedded memory, and 16 high-speed transceivers makes it a flexible ASIC prototyping platform where multi-million-gate ASIC designs must be validated before tape-out. Designers partition large ASICs across multiple Arria II GZ devices using TDM or chip-with-chip links, leveraging the 6.375 Gbps serial I/O for inter-FPGA connectivity. Quartus II synthesis flow and industry-standard verification IP shorten the bring-up cycle for complex SoC prototypes.
Recommended
Industrial Protocol Bridging
The EP2AGZ350FF35I3 bridges legacy industrial protocols like PROFIBUS, CAN, and RS-485 to modern Ethernet, PCIe, and Serial RapidIO backbones in factory automation systems. The industrial temperature grade (-40C to +100C Tj) supports deployment in harsh factory environments, while the 554 user I/O pins aggregate many fieldbus channels into a single bridging device. On-chip PCIe hard IP enables direct insertion into industrial PC backplanes without an external bridge chip.
Recommended
Recommended Products Summary
Engineering reference data for EP2AGZ350FF35I3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2AGZ350FF35C3N | EP2AGZ350FF35C4N | EP2AGZ350FF35C3G | EP2AGZ300FF35I3N |
|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (FF35) | 1152-ball FCBGA (FF35) - same | 1152-ball FCBGA (FF35) - same | 1152-ball FCBGA (FF35) - same | 1152-ball FCBGA (FF35) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 348,500 | 348,500 (same) | 348,500 (same) | 298,000 (-14.5%) | |
| Temperature Grade | Industrial (-40C to +100C Tj) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C Tj) | |
| Speed Grade | C3 (I3 = industrial C3 speed) | C3 (slower commercial) | C4 (faster commercial) | I3 (industrial C3 speed) | |
| Packaging Format | Tray | Tray | Tape & Reel | Tape & Reel | |
| Lifecycle Status | NRND | NRND | NRND | NRND | |
| Transceivers (max) | 16 channels at 6.375 Gbps | 16 channels at 6.375 Gbps | 16 channels at 6.375 Gbps | 16 channels at 6.375 Gbps |
Key Differentiators
- Highest logic density in Arria II GZ family (vs EP2AGZ300FF35I3N)
- Industrial temperature grade option (vs EP2AGZ350FF35C3N)
- Same 6.375 Gbps transceiver performance across all FF35 variants (vs EP2AGZ350FF35C4N)
Design Notes
The 1152-ball FCBGA FF35 package uses a 1.0 mm ball pitch and requires a minimum 4-layer PCB with microvia-in-pad technology for clean BGA escape. Plan inner layer stackup with dedicated GND planes on layers 2 and 5 to minimize return-path discontinuities under the BGA. Maintain at least 8 mil trace-and-space rules for 0.8 mm-pitch escape routing.
Flip-chip BGA packages dissipate heat primarily through the solder balls and PCB copper. At full transceiver utilization (16 channels at 6.375 Gbps) and high logic utilization, junction temperature can approach the +100C Tj industrial limit. Use thermal vias under the die and at least 4 oz² copper pours on outer layers directly beneath the BGA. Forced-air cooling is recommended for fan-out applications.
Transceiver reference clock jitter must stay below the 6.375 Gbps specification limit; use a low-jitter crystal oscillator (e.g., <1 ps RMS jitter at 12 kHz-20 MHz) and route the reference clock with controlled impedance and length matching. Place decoupling capacitors (0.1 uF, 10 uF, and 220 uF bulk) within 100 mils of every transceiver power pin to suppress switching noise.
Do not assume NRND parts have stable long-term supply. Build a safety stock and qualify a second-source FPGA family (Arria 10, Cyclone 10 GX) for designs entering production. Verify pin assignments in Quartus II pin planner before committing PCB layout because FF35 pinout maps differ from other Arria II GZ packages.
Compliance Information
RoHS and lead-free compliance per distributor listings. AEC-Q100 not applicable (this is an FPGA, not an automotive-qualified IC). Halogen-free status not specified in available data - set to unknown.
