EP2C35F672C8ES - Cyclone II FPGA 33K LE, 672-FBGA | Intel/Altera
MPN: EP2C35F672C8ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168 | $1,680.00 |
| 100 | $148.5 | $14,850.00 |
| 500 | $132 | $66,000.00 |
| 1,000 | $118 | $118,000.00 |
EP2C35F672C8ES Overview
A Field Programmable Gate Array (FPGA) is a programmable logic device that contains an array of configurable logic blocks (CLBs), interconnect, memory, and hard IP blocks such as PLLs, multipliers, and transceivers. FPGAs sit between general-purpose microcontrollers and ASICs in the system hierarchy: microcontrollers execute software sequentially, ASICs implement fixed logic, while FPGAs offer parallel, hardware-defined functionality that can be reconfigured at any point. Cyclone II specifically targets cost-sensitive, high-volume applications in the FPGA & CPLD product category within the broader Programmable Logic IC family. This part carries the commercial 0°C to 85°C operating range and supports core supply voltages around 1.2V, with PLL and I/O banks powered independently.
Key features of the EP2C35F672C8ES include support for LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards across 4 I/O banks, four general-purpose PLLs, and configuration via JTAG, serial passive, or Altera enhanced configuration devices. The Cyclone II architecture embeds Multiplier blocks that deliver up to 250 MHz DSP performance, along with M4K RAM blocks each supporting dual-port operation and FIFO mode. Dedicated per-pin signal integrity features such as on-chip termination (OCT) simplify board layout.
From a design perspective, the EP2C35F672C8ES is commonly used in industrial control, automotive infotainment, video processing, and communications infrastructure. Its 35 embedded 18x18 multipliers make it suitable for moderate-throughput DSP such as FIR filters or video scaling. Designers should note that the 'ES' suffix on the original MPN denotes an engineering sample - production builds typically use the EP2C35F672C8 (without ES). For new designs, confirm commercial-grade availability and lifecycle status.
When designing with this FPGA, ensure all four PLL supply pins (VCCA, VCCD_PLL) are properly decoupled with ferrite beads and bulk capacitance. The 672-ball FBGA requires 26mm x 26mm PCB area and microvia stack-up for reliable assembly. Use the Quartus II design software (latest service pack for legacy device support) for synthesis and place-and-route, and verify timing with the TimeQuest timing analyzer.
This page synthesizes current distributor stock levels, exact-spec drop-in alternatives from the Cyclone II family, and practical design notes not found in the bare manufacturer datasheet - intended for engineers evaluating legacy FPGA stock for production or redesign.
Drop-in alternatives for EP2C35F672C8ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C35F672C8ES (same form factor and footprint) — differing in Package, Operating Temperature, RoHS Status, Speed Grade, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C35F672C8
✅ Drop-In✓ In Stock
$71.85 / Unit
View Datasheet →EP2C35F672C7N
✅ Drop-In✓ In Stock
$98 / Unit
View Datasheet →EP2C35F672C6N
✅ Drop-In✓ In Stock
$122.5 / Unit
View Datasheet →EP2C35F484C8N
✅ Drop-In✓ In Stock
$65 / Unit
View Datasheet →EP2C35F484I8N
✅ Drop-In✓ In Stock
$56.01 / Unit
View Datasheet →EP2C35F672I8N
✅ Drop-In✓ In Stock
$98.5 / Unit
View Datasheet →EP2C35F672C8ES Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Process Technology | 90 nm CMOS |
| Logic Elements (LE) | 33,216 |
| Embedded Memory Bits | 483,840 bits |
| Embedded 18x18 Multipliers | 35 |
| Maximum User I/O Pins | 475 |
| Number of PLLs | 4 |
| Package | 672-ball FBGA (FineLine BGA), 26x26 mm |
| Logic Cells / Logic Blocks | 2100 |
| Operating Temperature | 0°C to +85°C (commercial) |
| Core Supply Voltage | 1.2 V |
| I/O Bank Count | 4 |
| Configuration Modes | JTAG, Passive Serial, Altera Enhanced |
| RoHS Status | Compliant |
| Memory Type | M4K RAM blocks (dual-port / FIFO) |
EP2C35F672C8ES 672-ball fbga (fineline bga), 26x26 mm Pin Configuration Guide
Pin configuration for EP2C35F672C8ES (672-ball fbga (fineline bga), 26x26 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C35F672C8ES.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C35F672C8ES is suitable for 6 applications: Industrial Motor Control, Video Processing and Image Pipeline, Telecommunications Baseband Processing, Automotive Infotainment and Driver Assistance, Test and Measurement Instrumentation, Medical Imaging Front-End Processing.
Industrial Motor Control
The EP2C35F672C8ES suits industrial motor-control systems where the 33,216 logic elements can host multiple PWM generators, encoder interfaces, and current-loop controllers concurrently. Its 35 embedded 18x18 multipliers handle Park/Clarke transforms for three-phase FOC algorithms at typical PWM frequencies of 10-20 kHz. The 672-ball FBGA package exposes 475 user I/Os - more than enough for parallel feedback channels, opto-isolated gate drivers, and debug ports. Compared with a microcontroller approach, the FPGA's deterministic latency eliminates jitter-induced torque ripple in precision servo systems, while the 90nm CMOS core keeps dynamic power manageable at industrial operating temperatures when the industrial-temp variant is selected.
Recommended
Video Processing and Image Pipeline
With 483,840 bits of embedded M4K RAM and 35 dedicated 18x18 multipliers, the EP2C35F672C8ES fits mid-throughput video processing pipelines such as deinterlacing, scaling, and color-space conversion at 480p/60fps. The four embedded PLLs generate pixel clocks and memory-controller clocks independently, while the 475 user I/Os support 24-bit RGB, ITU-R BT.656, and Camera Link interfaces. The Cyclone II architecture's parallel fabric offers 2-3x the throughput of microcontroller-based video preprocessing, and the BGA package's short bond wires keep LVDS signaling within the 500 Mbps budgets typical of consumer-grade displays.
Recommended
Telecommunications Baseband Processing
The EP2C35F672C8ES was widely deployed in early-generation wireless baseband cards, where its 33K LEs handle channelization, scrambling, and basic FEC encoding for sub-100 Mbps links. Its SSTL-2 I/O standard supports external DDR SDRAM memory for packet buffering, and the four PLLs provide the multiple clock domains needed for mixed-rate datapaths. For modern LTE/5G systems, this Cyclone II density is marginal, but for industrial RF links, point-to-point microwave backhaul, or legacy protocol bridges it remains cost-effective. Quartus II provides megafunctions for Viterbi decoding and Reed-Solomon FEC that map efficiently to the 35 multipliers and M4K RAM blocks.
Recommended
Automotive Infotainment and Driver Assistance
In early automotive infotainment platforms the EP2C35F672C8ES handled CAN/LIN gateway logic, media-stream routing, and rear-seat entertainment display processing concurrently. The 475 user I/Os accommodate multiple LVDS display links, MOST or Ethernet PHY interfaces, and GPIO for legacy vehicle networks. Its deterministic interrupt latency also suits early driver-assistance functions such as rear-view camera overlay and ultrasonic sensor fusion, where timing predictability matters more than peak throughput. For new automotive designs AEC-Q100-qualified Cyclone III (EP3C) or MAX 10 (10M04) families are preferred, but the EP2C35 remains in many production vehicles.
Recommended
Test and Measurement Instrumentation
Test equipment designers use the EP2C35F672C8ES for digital pattern generation, protocol decoding, and signal-conditioning logic where its 33K LEs implement wide state machines and parallel data paths. The 475 I/Os support multi-channel logic-analyzer front ends or arbitrary-waveform-generator sample interfaces, while the four PLLs synthesize the multiple clock domains required for clock-data recovery. Compared with ASIC implementations, the FPGA's reconfigurability lets one platform host multiple protocol decoders - I2C, SPI, UART, I2S, JTAG - with a single Quartus II bitstream swap, simplifying factory-floor test of varied DUTs.
Recommended
Medical Imaging Front-End Processing
Although not a medical-grade qualified part, the EP2C35F672C8ES has been used in ultrasound front-end beamforming and endoscopy image-acquisition subsystems where its 35 multipliers implement FIR filters and its M4K RAM buffers scan-line data in real time. The 475 I/Os connect to high-speed ADCs and provide parallel LVDS links to image processors. The four PLLs generate the multiple phase-aligned clocks needed for beamforming arrays. Designers should note that production medical devices typically require full IEC 60601 compliance and dedicated medical-grade FPGAs (e.g., Cyclone IV with extended validation), but for prototyping this Cyclone II density remains useful.
Recommended
Recommended Products Summary
Engineering reference data for EP2C35F672C8ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C35F672C8 | EP2C35F672C7N | EP2C35F672C6N | EP2C35F484C8N | EP2C35F484I8N | EP2C35F672I8N |
|---|---|---|---|---|---|---|---|
| Package | 672-ball FBGA | 672-ball FBGA - same | 672-ball FBGA - same | 672-ball FBGA - same | 484-ball FBGA - smaller | 484-ball FBGA - smaller | 672-ball FBGA - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Logic Elements | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 | 33,216 |
| Speed Grade | 8 | 8 | 7 (slower) | 6 (slowest) | 8 | 8 | 8 |
| Embedded Memory | 483,840 bits | 483,840 bits | 483,840 bits | 483,840 bits | 483,840 bits | 483,840 bits | 483,840 bits |
| Embedded Multipliers (18x18) | 35 | 35 | 35 | 35 | 35 | 35 | 35 |
| Maximum User I/O | 475 | 475 | 475 | 475 | ~322 (smaller package) | ~322 (smaller package) | 475 |
| Operating Temperature | 0°C to +85°C (Commercial) | 0°C to +85°C | 0°C to +85°C | 0°C to +85°C | 0°C to +85°C | -40°C to +100°C (Industrial) | -40°C to +100°C (Industrial) |
Key Differentiators
- Highest commercial-temp speed grade in Cyclone II 33K LE tier (vs EP2C35F672C7N)
- Same-family part with same die - guaranteed pin compatibility (vs EP2C35F484C8N)
- Engineering sample grade versus production grade (vs EP2C35F672C8)
Design Notes
The EP2C35F672C8ES requires multiple independent supply rails: VCCINT (1.2V core), VCCIO (1.5V/1.8V/2.5V/3.3V depending on bank standard), VCCA_PLL (1.2V analog PLL), and VCCD_PLL (1.2V digital PLL). Each PLL pair must be isolated with a ferrite bead and bulk-decoupled with 0.1uF + 10uF ceramics per pin, per the Cyclone II Device Handbook. Power sequencing is not strictly mandated for Cyclone II, but bringing up VCCINT before VCCIO prevents I/O latch-up. Estimated: total quiescent current for an empty design is ~30 mA on VCCINT at room temp, rising to ~500 mA with full logic utilization at high toggle rates.
The 672-ball FBGA package has a junction-to-ambient thermal resistance (theta_JA) of approximately 12 C/W with a standard 4-layer PCB and adequate thermal vias under the BGA. At full utilization (33K LEs at 100% toggle rate), internal dissipation can reach 1.5-2.0 W. Designers targeting industrial-temp operation should include a thermal copper pour on the top layer connected to the BGA's central thermal balls and verify with a thermal camera that junction temperature stays below 100°C. Cyclone II's 90nm process has higher leakage than modern nodes, so power modeling should account for both dynamic and static dissipation.
The 672-ball FBGA uses a 1.0 mm ball pitch on a 26x26 mm substrate, requiring microvia (laser-drilled or stacked-via) PCB technology for reliable assembly. Minimum trace width between balls is 0.5 mm with 0.2 mm clearance per IPC-7351. Power and ground balls should fan out on the top layer with via-in-pad for direct connection to inner planes; signal balls fan out to inner layers using microvia-in-pad. The BGA's center thermal balls must be soldered to a thermal pad with a continuous ground plane beneath for heat spreading and electrical return. Estimated: routing escape density is ~6 traces between adjacent ball rows using 4 mil line/space.
Cyclone II supports LVDS inputs and outputs on selected pins, with up to 640 Mbps data rates. According to the Cyclone II Device Handbook, LVDS pairs require 100 ohm differential impedance and matched trace lengths within 20 mils. SSTL-2 I/O for DDR SDRAM interfaces require matched-length fly-by topology with 50-ohm single-ended impedance. Use the on-chip termination (OCT) feature to eliminate external series resistors - the Cyclone II supports calibrated series, parallel, and differential OCT values, configurable in the Quartus II Assignment Editor.
Compliance Information
RoHS and lead-free confirmed per Altera/Intel Cyclone II product page. Not AEC-Q100 qualified - select the industrial-temp EP2C35F672I8N variant for non-automotive harsh environments; for automotive AEC-Q100 work use Cyclone III Auto or MAX 10 Auto families.
