EP2C70F672C6 - 68K-Cell Cyclone II FPGA, 672-FBGA | Altera
MPN: EP2C70F672C6 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $466.83 | $466.83 |
| 10 | $443.49 | $4,434.90 |
| 100 | $408.21 | $40,821.00 |
| 500 | $373.47 | $186,735.00 |
| 1,000 | $338.91 | $338,910.00 |
EP2C70F672C6 Overview
FPGAs (Field-Programmable Gate Arrays) are semiconductor devices that contain an array of programmable logic blocks, interconnect, and I/O elements which can be configured by the customer after manufacturing to implement custom digital circuits. FPGAs sit within the broader hierarchy of programmable logic devices (PLD), alongside CPLDs, and are widely used for digital signal processing, glue logic, ASIC prototyping, and parallel processing tasks. They are typically deployed via hardware description languages such as Verilog or VHDL, then synthesized and routed using vendor tooling.
Key features of the EP2C70F672C6 include 422 maximum user I/O pins, 1,152,000 bits of embedded RAM (approximately 1.1 Mbit), four PLLs for clock management, and support for external memory interfaces such as DDR, DDR2, SDR, and QDRII SRAM. The 'C6' speed grade places the part in a moderate performance tier suitable for industrial-grade temperature operation, while the 'F672' package suffix designates the 672-pin FBGA.
The Cyclone II architecture combines 4-input LUT-based logic elements with embedded M9K memory blocks and DSP-style multiplier blocks. The 90 nm low-k process enables the device to deliver high logic density at low static power while sustaining 500 MHz internal operation, making it well-suited for cost-sensitive volume production across consumer, industrial, and communications segments.
Typical applications include motor control, video processing, industrial automation controllers, ASIC prototyping, communications infrastructure line cards, and embedded computing platforms. Designers often pair the EP2C70F672C6 with external DDR memory, high-speed ADCs/DACs, and PHY devices to build complete digital signal processing pipelines.
When designing with this FPGA, ensure PCB layout supports the high pin-count BGA footprint with appropriate via-in-pad or microvia technology for reliable soldering. Plan power-rail sequencing for the 1.2 V core and I/O banks, and use the Quartus II design toolchain for synthesis, placement, and routing. Verify timing closure against the C6 speed grade before tape-out.
Drop-in alternatives for EP2C70F672C6 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C6 (same form factor and footprint) β differing in Package, Speed Grade, Configuration Modes, Process Technology, RoHS Status.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2C70F672C6N
β Drop-Inβ In Stock
$178.3 / Unit
View Datasheet βEP2C70F672C7N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$195 / Unit
View Datasheet βEP2C70F672C8
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$238.2 / Unit
View Datasheet βEP2C50F672C6
β Drop-Inβ In Stock
$55.95 / Unit
View Datasheet βEP2C50F672C6N
β Drop-Inβ In Stock
$119 / Unit
View Datasheet βEP4CE75F672C8N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2C70F672C6 Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Process Technology | 90 nm CMOS |
| Logic Elements | 68,416 |
| Configurable Logic Blocks (CLBs) | 4,276 |
| Maximum User I/O | 422 |
| Embedded Memory | 1,152,000 bits (~1.1 Mbit) |
| Embedded Memory Blocks | M9K blocks |
| PLLs | 4 |
| Core Voltage | 1.2 V |
| Maximum Internal Frequency | 500 MHz |
| Speed Grade | C6 |
| Package | 672-ball FBGA (F672) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (0C to +85C) |
| External Memory Interface Support | DDR, DDR2, SDR, QDRII SRAM |
| RoHS Status | Unknown - requires confirmation from manufacturer |
EP2C70F672C6 Pin Configuration
| Pin 1 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 100 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 200 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 300 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 400 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 500 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 600 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
| Pin 672 | IO / VCC / GND β User I/O or power/ground ball (refer to datasheet pin table for specific assignment) |
Typical Applications
EP2C70F672C6 is suitable for 6 applications: Industrial Motor Control, Video Processing and Image Pipeline, ASIC Prototyping and Emulation, Communications Infrastructure Line Cards, Embedded Computing Platform, Test and Measurement Instrumentation.
Industrial Motor Control
The EP2C70F672C6's 68,416 logic elements and 422 user I/O pins make it well-suited for multi-axis industrial motor control platforms requiring parallel processing of encoder feedback, PWM generation, and current sensing. The four integrated PLLs enable precise timing of field-oriented control (FOC) loops at high PWM frequencies, while the 1.1 Mbit of embedded RAM buffers control parameters and state variables. The C6 speed grade sustains the computational throughput needed for torque-loop calculation at 10-20 kHz switching rates.
Recommended
Video Processing and Image Pipeline
The EP2C70F672C6's 422 I/O pins support wide parallel video buses for real-time image processing in surveillance, broadcast, and machine vision systems. The 1.1 Mbit of embedded RAM buffers line-scan data and intermediate filter results, while the embedded multipliers accelerate convolution kernels and color-space conversion. The DDR/DDR2 memory controller interfaces connect to external frame buffers for full-HD resolution pipelines at typical 60-100 MHz pixel rates.
Recommended
ASIC Prototyping and Emulation
With 68,416 logic elements and 422 user I/O pins, the EP2C70F672C6 serves as a cost-effective ASIC prototyping vehicle for designs targeting gate counts below 70K equivalent ASIC gates. The Cyclone II architecture supports multi-clock domain designs and the embedded M9K memory blocks emulate SRAM macros common in ASICs. Quartus II synthesis flow accepts standard Verilog or VHDL inputs and produces timing-accurate reports against the C6 speed grade.
Recommended
Communications Infrastructure Line Cards
Telecom line cards benefit from the EP2C70F672C6's combination of high logic density, four PLLs, and DDR/QDRII memory interface support. The device bridges between serial backplanes and parallel data paths, performs framing/deframing, and implements protocol termination logic. The 672-FBGA package provides the signal integrity required for 100+ MHz parallel buses interfacing to network processors and PHYs.
Recommended
Embedded Computing Platform
The EP2C70F672C6 can host soft-core processors such as Altera Nios II alongside custom peripherals, building complete embedded computing platforms. The 1.1 Mbit embedded RAM serves as cache and DMA buffer, while the DDR/DDR2 controllers connect to external program memory. The 422 I/O pins interface to Flash, Ethernet PHYs, UARTs, and GPIO, enabling single-chip SoC replacements in cost-sensitive applications.
Recommended
Test and Measurement Instrumentation
The EP2C70F672C6's 500 MHz internal frequency and embedded multiplier blocks enable custom logic-analyzer, pattern-generator, and protocol-analyzer instrument designs. The four PLLs generate the multiple precise clock domains required for stimulus generation and response capture. The 422 user I/O pins connect to high-speed ADCs/DACs and probe fixtures, while the DDR memory interface buffers deep acquisition traces.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C6 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C6N | EP2C70F672C7N | EP2C50F672C6 | EP4CE75F672C8N |
|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 672-FBGA (F672) | 672-FBGA (F672) - same | 672-FBGA (F672) - same | 672-FBGA (F672) - same | 672-FBGA (F672) - same |
| Logic Elements | 68,416 | 68,416 | 68,416 | 50,316 (-26%) | 75,408 (+10%) |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Speed Grade | C6 | C6 | C7 (slower) | C6 | C8 (slower) |
| RoHS Lead-Free | Unknown | Yes | Yes | Unknown | Yes |
Key Differentiators
- Highest logic density in Cyclone II family with same package footprint (vs EP2C50F672C6)
- RoHS lead-free compliance option in same package (vs EP2C70F672C6N)
- Migration path to higher-density Cyclone IV generation (vs EP4CE75F672C8N)
Design Notes
The 672-FBGA package requires multi-layer PCB construction with either via-in-pad or microvia technology for reliable soldering. Estimate: BGA pitch is 1.0 mm typical for Cyclone II F672, requiring minimum 0.4 mm laser-drilled vias and 4-layer stackup with continuous ground planes under the device. Decoupling capacitors should be placed on the opposite PCB side directly beneath the package, with 0402-size 0.1 uF and 10 uF combinations covering all power balls.
Power sequencing for the EP2C70F672C6 requires the 1.2 V VCCINT to ramp before or simultaneously with the VCCIO bank voltages. According to the Cyclone II handbook, failure to observe proper sequencing can cause permanent device damage through latch-up. Use a power supervisor IC with adjustable delay to enforce the required 100 ms minimum delay between VCCINT and VCCIO ramp completion.
Route DDR/DDR2 memory interfaces with matched-length traces (within +/- 50 mil) and 50 ohm controlled impedance. The Cyclone II DQS phase-shift circuitry requires precise delay matching between DQS and DQ signals; use serpentine routing to tune lengths. Place external memory devices as close as possible to the dedicated DQS pins on the FPGA to minimize reflections.
Estimated: At 500 MHz internal frequency with 70% logic utilization, the EP2C70F672C6 dissipates approximately 1.5-2.0 W typical. The 672-FBGA package has theta_JA of approximately 15-20 C/W with proper PCB thermal design. For continuous operation at elevated ambient temperatures, include thermal vias beneath the package and consider a small heatsink if junction temperature exceeds 85C in worst-case corner analysis.
Verify configuration mode selection (AS, PS, JTAG, or Fast Passive Parallel) matches the design intent before PCB fab - incorrect MSEL pin strapping is a common bring-up failure. The Cyclone II requires proper CONF_DONE and nSTATUS pull-up to 3.3 V; omit these and configuration will fail silently. Use Quartus II programmer to verify IDCODE matches before attempting full configuration.
Compliance Information
RoHS/REACH compliance not confirmed in retrieved data - the EP2C70F672C6N is the documented RoHS-compliant variant per FindIC comparison data. Last-time-buy lifecycle status means new compliance certifications are unlikely. AEC-Q100 not applicable for FPGAs in automotive safety-critical roles.
