EP2C70F672C6N - Cyclone II FPGA, 68K LE, 672-BGA | Intel/Altera
MPN: EP2C70F672C6N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $237.74 | $237.74 |
| 10 | $225.85 | $2,258.50 |
| 25 | $213.97 | $5,349.25 |
| 100 | $196.32 | $19,632.00 |
| 250 | $178.3 | $44,575.00 |
EP2C70F672C6N Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device consisting of an array of configurable logic blocks (CLBs / LABs), programmable routing, embedded memory blocks, and hard IP such as PLLs and transceivers, all governed by SRAM-based configuration memory. FPGAs sit in the broader semiconductor hierarchy as programmable logic devices between fixed-function ASICs and software-driven microprocessors, offering hardware-timed parallelism with on-the-fly reconfigurability. The Cyclone II family specifically targets low-cost, high-volume applications with a 90 nm process and an architecture optimized for logic density per dollar.
The EP2C70F672C6N features 4,276 logic array blocks (LABs), 150 embedded 18x18 multipliers for DSP operations, and four phase-locked loops (PLLs) for clock management. Its 1,152,000 bits of embedded RAM are arranged in M4K blocks supporting true dual-port, single-port, and FIFO modes. The device supports LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards through 422 user I/O pins distributed across eight I/O banks, enabling flexible mixed-voltage interfacing with external memories, microprocessors, and high-speed peripherals.
Cyclone II architecture is built on a 90 nm low-k dielectric CMOS process with copper interconnect, delivering a balance of static power, dynamic performance, and logic density. Internal configuration is stored in SRAM and loaded from external flash or a configuration controller, allowing in-field updates and design iterations. The 672-pin FineLine BGA package provides sufficient ball density for full I/O utilization while maintaining manageable PCB routing with 1.0 mm ball pitch.
Typical applications for this part include industrial motor control, video processing pipelines, low-cost protocol bridging, embedded vision, telecom line cards, and education/hobby prototyping boards. The combination of embedded multipliers and significant logic density supports DSP workloads such as FIR filtering and image preprocessing without requiring external DSP devices.
When designing with EP2C70F672C6N, ensure the configuration scheme (typically AS or JTAG) and clock distribution are planned before PCB layout; the 672-BGA package requires careful fanout planning with microvia or via-in-pad technology on lower-layer PCBs. Power estimation should account for the dynamic power of the 68K logic elements plus the static power of the SRAM configuration memory, and decoupling must follow Intel/Altera's Cyclone II handbook recommendations.
This page synthesizes distributor pricing, drop-in alternatives across the Cyclone II family, and practical design notes not found in the manufacturer datasheet alone - useful for both new designs and legacy EOL substitution.
Drop-in alternatives for EP2C70F672C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C6N (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, RoHS Status, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C70F672C6
✅ Drop-In✓ In Stock
$338.91 / Unit
View Datasheet →EP2C70F672C7N
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$239.75 / Unit
View Datasheet →EP2C70F672C5N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP2C50F672C6N
✅ Drop-In✓ In Stock
$119 / Unit
View Datasheet →EP2C35F672C6N
✅ Drop-In✓ In Stock
$122.5 / Unit
View Datasheet →EP2C70F672C6N Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Logic Elements | 68,416 |
| Number of LABs/CLBs | 4,276 |
| Total RAM Bits | 1,152,000 |
| Maximum User I/O | 422 |
| Embedded 18x18 Multipliers | 150 |
| PLLs | 4 |
| Package | 672-BGA (FBGA-672), FineLine BGA |
| Pin/Package Code | F672 |
| Speed Grade | 6 (C6) |
| Operating Temperature | 0C to 85C (Commercial) |
| Process Technology | 90 nm CMOS, low-k dielectric |
| Configuration Memory | SRAM-based (volatile) |
| I/O Standards Supported | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| RoHS Status | Compliant (lead-free per datasheet) |
| Supply Voltage (Core) | 1.2 V |
| Mounting Type | Surface Mount (BGA) |
EP2C70F672C6N f672 Pin Configuration Guide
Pin configuration for EP2C70F672C6N (f672 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C70F672C6N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C70F672C6N is suitable for 6 applications: Industrial Motor Control (FOC / PWM), Video Processing / Image Pipeline, Telecom Line Card / Protocol Bridging, Embedded Vision / Machine Vision Preprocessing, DSP / FIR Filter Acceleration, Education / Hobby FPGA Development Boards.
Industrial Motor Control (FOC / PWM)
The EP2C70F672C6N's 68,416 logic elements and 150 embedded 18x18 multipliers are well matched to field-oriented control (FOC) loops for three-phase AC induction and permanent-magnet servo motors. The 422 user I/Os accommodate multiple ADC channels for current sensing, resolver/encoder interfaces, gate-driver PWM outputs, and industrial communication peripherals (EtherCAT, CAN, RS-485) on a single device. The 4 PLLs derive the high-frequency switching clocks from a low-jitter external reference, while 1,152,000 RAM bits buffer state-variable tables and look-up tables for sine/cosine transforms. Designers should note that industrial temperature grades require the I-suffix variant (EP2C70F672I6N), since this C-grade part is specified 0C to 85C.
Recommended
Video Processing / Image Pipeline
The EP2C70F672C6N's 1,152,000 RAM bits arranged in M4K blocks are ideal for line-buffer storage in video pipelines, supporting true dual-port operation at common video clock rates. The 150 18x18 multipliers implement real-time FIR filters, color-space conversion matrices, and scaling kernels without external DSP assistance. With 422 user I/Os, the device can ingest parallel ITU-R BT.656 / BT.1120 video streams, drive HDMI transmitters through LVDS pairs, and host local control channels. The 672-FBGA package provides sufficient ball density for the wide parallel buses typical in mid-resolution image processing, while the 90 nm Cyclone II architecture balances cost against sufficient throughput for SD/HD pipelines.
Recommended
Telecom Line Card / Protocol Bridging
Telecom line cards and protocol bridges benefit from the EP2C70F672C6N's combination of 422 user I/Os and four PLLs, which can simultaneously clock multiple independent interfaces such as TDM buses, SPI/QSPI control planes, and LVDS backplanes. The 1,152,000 embedded RAM bits provide per-channel buffer memory for traffic shaping, while 150 multipliers handle forward-error-correction (FEC) and scrambling functions on aggregate data. The 672-FBGA FineLine BGA package is compatible with standard telecom-grade PCB stackups using 1.0 mm pitch BGA fan-out rules. The commercial 0C to 85C grade suits temperature-controlled CO environments, and the NRND status should be weighed against long-term availability for new telecom deployments.
Recommended
Embedded Vision / Machine Vision Preprocessing
The EP2C70F672C6N supports entry-to-mid-tier embedded vision tasks such as thresholding, blob detection, and convolution kernels at modest frame rates. Its 150 embedded 18x18 multipliers implement 2D convolution filters for edge detection and noise reduction, while the 1,152,000 RAM bits store frame buffers for inter-frame processing. The 422 user I/Os accommodate parallel CMOS image sensor interfaces, MIPI-to-parallel bridge outputs, and host processor handshaking. Designers targeting higher resolutions or real-time deep-learning inference should evaluate Cyclone V or Cyclone 10 LP families for greater logic density and lower power; for legacy designs and cost-sensitive vision modules, the EP2C70F672C6N remains a workable solution.
Recommended
DSP / FIR Filter Acceleration
The 150 embedded 18x18 multipliers of the EP2C70F672C6N enable hardware acceleration of FIR filters, IIR filters, and FFT butterfly operations in audio, communications, and instrumentation DSP chains. Multipliers can be cascaded with 4,276 LAB registers to build systolic FIR architectures achieving sample rates well above 200 MHz in the C6 speed grade. The 1,152,000 RAM bits hold coefficient tables and circular delay-line samples for long-tap filters, while 422 I/Os expose parallel data paths to external ADCs and DACs. For new DSP designs, designers should compare against dedicated DSP devices or Cyclone V with hardened DSP blocks, but for embedded FPGA+DSP systems the EP2C70F672C6N is a proven workhorse.
Recommended
Education / Hobby FPGA Development Boards
The EP2C70F672C6N has historically appeared in DE2-70 and similar university FPGA development kits, providing 68,416 logic elements for teaching digital design, computer architecture (CPU cores, pipelining), and HDL synthesis. Its 422 user I/Os, four PLLs, and 1,152,000 RAM bits support student projects ranging from VGA controllers and simple soft-core CPUs to audio synthesizers and SDR receivers. The 672-FBGA package is impractical for hand-soldering, so development boards typically include pre-routed PCBs. Given the NRND status of Cyclone II, instructors should evaluate transitioning curricula to Cyclone IV or Cyclone 10 LP boards; the EP2C70F672C6N remains valuable for maintaining existing lab kits.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C6 | EP2C70F672C7N | EP2C70F672C8N | EP2C70F672C5N | EP2C50F672C6N | EP2C35F672C6N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-BGA (FBGA-672, F672) | 672-BGA (FBGA-672, F672) - same | 672-BGA (FBGA-672, F672) - same | 672-BGA (FBGA-672, F672) - same | 672-BGA (FBGA-672, F672) - same | 672-BGA (FBGA-672, F672) - same | 672-BGA (FBGA-672, F672) - same |
| Family | Cyclone II | Cyclone II | Cyclone II | Cyclone II | Cyclone II | Cyclone II | Cyclone II |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 50,560 (-26%) | 35,016 (-49%) |
| Speed Grade | C6 | C6 | C7 (faster) | C8 (fastest) | C5 (slower) | C6 | C6 |
| Operating Temperature | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) | 0C to 85C (Commercial) |
| Terminal Finish | Lead-free (Pb-free, RoHS) | Leaded (SnPb) | Lead-free (Pb-free, RoHS) | Lead-free (Pb-free, RoHS) | Lead-free (Pb-free, RoHS) | Lead-free (Pb-free, RoHS) | Lead-free (Pb-free, RoHS) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Cost-optimized speed grade in high-density Cyclone II (vs EP2C70F672C7N)
- Lead-free RoHS terminal finish (vs EP2C70F672C6)
- Highest logic density in Cyclone II F672 BGA (vs EP2C50F672C6N)
Design Notes
The 672-FBGA FineLine BGA package uses a 1.0 mm ball pitch, which requires either microvia (laser-drilled) stack-up or via-in-pad technology on inner layers for reliable fan-out. A 4-layer PCB with 0.5 oz copper and FR-4 substrate is typical, but production designs targeting the 422 user I/Os at maximum LVDS rates should use 6 layers to control impedance and reduce crosstalk. Decoupling must follow the Cyclone II device handbook's recommended network: 0.1 uF and 0.01 uF ceramic caps placed within 100 mils of each VCC pin, plus bulk 10 uF to 100 uF tantalum or polymer caps per voltage rail. Ground returns should be a continuous low-impedance plane directly beneath the BGA field; avoid routing signal traces beneath the package.
Power estimation for the EP2C70F672C6N requires the Cyclone II PowerPlay Early Power Estimator spreadsheet because static and dynamic power vary widely with utilization, toggle rate, and clock frequency. At typical 50% logic utilization with 100 MHz clocks and 50% toggle rate, expect approximately 1.5 W to 2.5 W of dynamic power plus approximately 0.3 W static, totaling around 2 W to 3 W. The 1.2 V core rail must be sourced from a low-noise LDO or DC-DC converter with output ripple below 30 mVpp to meet datasheet jitter specifications; the 2.5 V and 3.3 V analog/auxiliary rails are less sensitive. Thermal design should assume 1.0 C/W junction-to-ambient on a properly designed 4-layer PCB with adequate copper flood.
Do not assume Cyclone II parts are interchangeable with Cyclone IV or Cyclone V on the same PCB footprint - ball maps and I/O bank voltages differ between generations. Configuration mode selection (AS, PS, JTAG, or Fast Passive Parallel) must be set correctly via MSEL pins before power-up; mismatched MSEL settings cause configuration failures that look like silicon defects. The JTAG TCK frequency should not exceed 33 MHz in compliance mode, and TCK must have a pull-up to VCCIO of the JTAG bank. SRAM-based configuration means the device loses its bitstream at power-down; external configuration memory (EPCS4, EPCS16, or compatible) is mandatory for standalone operation. Finally, always include a reset supervisor on the nCONFIG / nSTATUS lines to recover from brown-out events during in-field updates.
Compliance Information
RoHS compliance confirmed by 'N' suffix and datasheet lead-free designation per Altera/Intel product page. Cyclone II family is not AEC-Q100 qualified; automotive applications should evaluate Cyclone IV automotive variants or dedicated automotive FPGA families.
