EP2C70F672C7 - Cyclone II FPGA 68K LE 672-BGA | Intel
MPN: EP2C70F672C7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $385.32 | $385.32 |
| 10 | $360.5 | $3,605.00 |
| 100 | $332 | $33,200.00 |
| 250 | $305 | $76,250.00 |
| 500 | $278 | $139,000.00 |
EP2C70F672C7 Overview
An FPGA (Field-Programmable Gate Array) is a class of programmable logic device that allows designers to implement custom digital circuits using a matrix of configurable logic blocks (CLBs), embedded memory blocks, multipliers, and programmable interconnect. FPGAs sit between general-purpose microcontrollers and fixed-function ASICs in the design hierarchy: more flexible than an ASIC, but faster and more deterministic than a software-driven processor. The Cyclone II family specifically targets cost-sensitive, high-volume applications where designers need ASIC-like integration without the NRE mask charges.
Key features of the EP2C70F672C7 include 150 embedded 18x18 multipliers (approximately 300 9x9 multipliers), four PLLs for clock management, and support for external memory interfaces such as DDR, DDR2, SDRAM, and QDRII SRAM. The device delivers up to 500 MHz internal performance per the manufacturer datasheet and supports configuration via passive serial (PS), active serial (AS), and JTAG modes, with built-in decompression and encryption for bitstream security.
Architecturally, the Cyclone II device uses a lookup-table (LUT)-based logic fabric with embedded M4K memory blocks (each 4 Kbits, configurable as RAM, ROM, or shift register) and dedicated multiplier blocks for DSP functions. The 90 nm process balances cost, density, and static power, making it well suited for video processing, industrial control, and communications infrastructure designs.
Typical applications include digital video surveillance, industrial machine vision, motor control, software-defined radio front-ends, protocol bridging in telecom equipment, and ASIC prototyping. The high logic density and embedded multipliers also make it suitable for image processing pipelines and low-to-mid complexity DSP workloads.
When designing with this part, pay close attention to power sequencing: the 1.2 V VCCINT, 2.5 V VCCAUX, and I/O VCCIO rails must come up in a defined order to prevent I/O bus contention. Use the Altera/Intel Quartus II design software (legacy support) for synthesis, place-and-route, and timing closure. The 672-BGA package requires careful PCB layout with microvia or via-in-pad technology for reliable assembly.
Drop-in alternatives for EP2C70F672C7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C7 (same form factor and footprint) — differing in Package, Speed Grade, RoHS Status, Process Technology, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C70F672C7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$238.2 / Unit
View Datasheet →EP2C70F672C6
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$338.91 / Unit
View Datasheet →EP2C70F672I7
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP2C70F672I8
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$185 / Unit
View Datasheet →EP2C70F672C7 Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Logic Elements | 68,416 |
| Configurable Logic Blocks (CLBs) | 4,276 LABs |
| Embedded Memory Bits | 1,152,000 bits (1152 Kbit) |
| Embedded 18x18 Multipliers | 150 |
| PLLs | 4 |
| Maximum User I/O | 422 |
| Process Technology | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.2 V |
| Auxiliary Voltage (VCCAUX) | 2.5 V |
| Internal Frequency | Up to 500 MHz |
| Package | 672-ball FineLine BGA (FBGA-672) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (Commercial) |
| Configuration Modes | Passive Serial, Active Serial, JTAG |
| Lead Free | Yes |
| RoHS Status | Compliant |
EP2C70F672C7 672-ball fineline bga (fbga-672) Pin Configuration Guide
Pin configuration for EP2C70F672C7 (672-ball fineline bga (fbga-672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C70F672C7.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C70F672C7 is suitable for 6 applications: Industrial Machine Vision, Digital Video Surveillance, Motor Control and Industrial Automation, Software-Defined Radio Front-End, ASIC Prototyping and Emulation, Display Controllers and Video Walls.
Industrial Machine Vision
The EP2C70F672C7 fits machine vision pipelines thanks to its 150 embedded 18x18 multipliers and 1,152 Kbits of embedded RAM, which together handle real-time Sobel, Laplacian, or convolution kernels on VGA-to-720p image streams at 60 fps. With 68,416 logic elements, designers can implement custom preprocessing (debayering, gamma correction) alongside the DSP stage without resorting to an external DSP chip. The 4 PLLs allow independent timing domains for the camera sensor, DDR2 frame buffer, and LVDS display output. Per the Cyclone II handbook, the FPGA's LVDS I/O support enables direct connection to industrial Camera Link or MIPI adapters.
Recommended
Digital Video Surveillance
The EP2C70F672C7's logic density makes it well suited to multi-channel H.264 or MJPEG encoding for IP camera designs, where 68K LEs can implement motion estimation, entropy coding, and a hardware crypto block for TLS simultaneously. The 422 user I/O pins support multiple video input streams (BT.656, HDMI receiver I2S, or parallel LVCMOS) plus a Gigabit Ethernet MAC interface without external bus muxes. The 1.2 V core and 90 nm process keep typical board power under 3 W even at full utilization, which is critical for fanless PoE-powered camera enclosures. Intel's reference designs in AN 433 and AN 480 demonstrate complete surveillance pipelines on this exact family.
Recommended
Motor Control and Industrial Automation
The EP2C70F672C7's combination of high-speed multipliers and abundant logic supports field-oriented control (FOC) loops for three-phase AC motors and stepper drives at switching frequencies up to 100 kHz. Its hardware multipliers execute Clarke and Park transforms plus PID calculations within 2-3 us per PWM cycle, leaving headroom for encoder feedback decoding and CANopen or EtherCAT communication stacks. The four PLLs derive precise PWM and ADC-sampling clocks from a single crystal. With industrial temperature siblings (I7 grade) sharing the same BGA pinout, designs can be qualified for factory-floor environments without PCB rework.
Recommended
Software-Defined Radio Front-End
The EP2C70F672C7 implements digital down-conversion (DDC), digital up-conversion (DUC), and baseband processing for narrowband SDR receivers up to 50 MHz of instantaneous bandwidth. With 150 18x18 multipliers, the device runs multiple parallel FIR and CORDIC channels while the 1,152 Kbits of block RAM serves as a sample buffer between the ADC and the host processor. The LVDS I/O pairs accept high-speed ADC data (e.g., 14-bit ADCs at 100 MSPS) directly without external deserialization. Per Altera application note AN 443, the Cyclone II family was a reference platform for low-cost SDR designs including FM, DAB, and amateur radio transceivers.
Recommended
ASIC Prototyping and Emulation
With 68,416 logic elements and 1,152 Kbits of embedded memory, the EP2C70F672C7 emulates mid-complexity ASICs containing ARM-compatible cores, custom peripherals, and memory controllers before tape-out. Multiple FPGAs can be ganged on a custom PCB using LVDS-based inter-chip links, achieving effective logic densities above 200K LEs per board. The Quartus II software provides RTL-level debug, logic-analyzer signal tap, and gate-level timing closure that matches silicon behavior within 10-15% on critical paths. This makes the EP2C70F672C7 a staple in early-stage ASIC validation labs and university VLSI courses.
Recommended
Display Controllers and Video Walls
The EP2C70F672C7 drives multi-panel LCD or LED video walls by capturing DVI/HDMI input, performing color-space conversion, scaling, and edge-blending, then outputting to multiple LVDS or TTL display channels simultaneously. The 422 user I/O pins accept high-pixel-rate LVDS inputs (up to 840 Mbps per pair) and drive four or more 1080p outputs through the FPGA's on-chip serializers. The 4 PLLs provide independent pixel clocks for each output panel, eliminating the need for external clock buffers. The embedded multipliers accelerate image scaling and sharpening filters with minimal logic overhead.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C7N | EP2C70F672C8 | EP2C70F672C6 | EP2C70F672I7 | EP2C70F672I8 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-FBGA | 672-FBGA | 672-FBGA | 672-FBGA | 672-FBGA | 672-FBGA |
| Speed Grade | C7 (fastest) | C7 | C8 (one bin slower) | C6 (two bins slower) | I7 (industrial, C7 speed) | I8 (industrial, C8 speed) |
| Temperature Grade | Commercial (0C to +85C) | Commercial | Commercial | Commercial | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 |
| Embedded RAM (Kbit) | 1,152 | 1,152 | 1,152 | 1,152 | 1,152 | 1,152 |
| Embedded 18x18 Multipliers | 150 | 150 | 150 | 150 | 150 | 150 |
| User I/O (max) | 422 | 422 | 422 | 422 | 422 | 422 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Largest density in the Cyclone II family (vs EP2C50F484C8N)
- Fastest speed grade (C7) within Cyclone II (vs EP2C70F672C8)
- Industrial temperature option with identical pinout (vs EP2C70F672I7)
Design Notes
The EP2C70F672C7 requires three power rails: VCCINT (1.2 V core), VCCAUX (2.5 V auxiliary for PLLs and configuration), and per-bank VCCIO (1.5/1.8/2.5/3.3 V). Per the Cyclone II handbook, VCCAUX must reach 2.5 V before or simultaneously with VCCINT to prevent latch-up; VCCIO can come up any time after VCCINT is stable. Use a sequenced power-supply IC such as the LTC3026 or TI TPS74401 with Power-Good signals to enforce this order. Decoupling: place 0.1 uF X7R capacitors within 100 mil of every VCCINT pin, plus a 10 uF bulk capacitor per voltage plane.
The 672-ball FineLine BGA has a 1.0 mm pitch and a 27 mm x 27 mm body. PCB design requires microvia technology (laser-drilled stacked vias or via-in-pad) for the inner signal rows; standard through-hole vias are too large to fan-out from the inner balls. Per Altera's AN 114 and the Cyclone II board design guidelines, route all signals on inner layers with controlled impedance (50 ohm single-ended, 100 ohm differential for LVDS). Maintain a continuous reference plane under the BGA and stitch the BGA ground balls to the inner ground plane with at least 9 via connections to minimize return-path inductance.
Common pitfalls with the EP2C70F672C7: (1) Using the wrong configuration mode - selecting AS (Active Serial) without providing a valid EPCS serial flash will leave the FPGA unconfigured. (2) Forgetting to drive the MSEL[3:0] pins with the correct mode-select pattern (e.g., 0000 for AS standard, 0100 for AS fast). (3) Assuming JTAG configuration will work without connecting TRST to VCCAUX via a 1-10 kohm pull-up - leaving TRST floating causes JTAG chain failures. (4) Driving LVDS inputs without 100-ohm differential termination at the FPGA pin - missing termination causes bit errors and reflected waveforms.
Estimated: at 100% logic utilization with all 150 multipliers active at 250 MHz toggle rate and a 50% switching activity assumption, the EP2C70F672C7 dissipates roughly 2.0-2.5 W. With the 672-FBGA's junction-to-ambient thermal resistance (theta_JA) of approximately 14 C/W (still air, JEDEC test board), this yields a junction temperature rise of 28-35 C above ambient. For commercial-temperature designs (0C to +85C), 1-2 m/s of airflow is recommended when utilization exceeds 70%; without airflow, derate the operating frequency by 20-30% or upgrade to the industrial-grade I7 sibling in the same package.
Compliance Information
RoHS compliant per DigiKey product listing (lead-free finish). Halogen-free status not explicitly stated in provided data; marked as unknown. Not AEC-Q100 qualified - the device is a commercial-grade FPGA, not an automotive-qualified part.
