EP2C70F672C8KK - Cyclone II FPGA 68K LE 672-FBGA | Intel
MPN: EP2C70F672C8KK ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $235 | $23,500.00 |
| 500 | $210 | $105,000.00 |
| 1,000 | $195 | $195,000.00 |
EP2C70F672C8KK Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as block RAM, DSP blocks, PLLs, and high-speed transceivers. Within the broader taxonomy, FPGAs sit under programmable logic devices (PLDs), which in turn belong to the digital logic IC family and the larger power management and logic semiconductor hierarchy. Cyclone II is positioned as a low-cost, high-volume FPGA family targeting consumer, industrial, communications, and video/imaging applications.
Key features of the EP2C70F672C8KK include 250 MHz maximum internal operating frequency on logic, support for external memory interfaces such as DDR/DDR2/QDRII SRAM, and 4 phase-locked loops (PLLs) for clock management. The device also provides up to 16 global clock networks, 8 dedicated clock pins, and supports hot-socketing and remote update via the Active Serial (AS) configuration scheme. The C8 speed grade indicates an 8 ns pin-to-pin logic delay.
Architecture details: the LE contains a 4-input look-up table (LUT), a programmable register, a carry chain, and a register chain. Embedded multiplier blocks (18x18) enable efficient DSP operations such as FIR filters and FFTs without consuming general-purpose logic. The 672-pin flip-chip BGA package supports high I/O count with controlled impedance for LVDS signaling up to several hundred Mbps.
Typical applications include video surveillance and image processing, industrial motor control, automotive infotainment prototypes, software-defined radio front-ends, and embedded control planes for communications equipment. The Cyclone II family remains popular for cost-sensitive legacy designs and university teaching labs.
When designing with this device, plan for a multi-rail power tree (1.2 V core, 2.5 V/3.3 V PLL analog, and per-bank VCCIO), proper BGA breakout routing with microvia stack-ups, and a configuration memory such as the EPCS16 or EPCS64 serial flash. The Quartus II design software (legacy) or the Quartus Prime Lite Edition is required for synthesis, place-and-route, and bitstream generation.
This page consolidates distributor pricing, same-package drop-in alternatives within the Cyclone II family, and practical design notes that go beyond the manufacturer datasheet for engineers evaluating or maintaining Cyclone II designs.
Drop-in alternatives for EP2C70F672C8KK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C8KK (same form factor and footprint) — differing in Package, Speed Grade, Process Technology, RoHS Status, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C70F672C8
✅ Drop-In✓ In Stock
$238.2 / Unit
View Datasheet →EP2C70F672C7N
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C7
✅ Drop-In✓ In Stock
$278 / Unit
View Datasheet →EP2C70F672C6N
✅ Drop-In✓ In Stock
$178.3 / Unit
View Datasheet →EP2C70F672C6
✅ Drop-In✓ In Stock
$338.91 / Unit
View Datasheet →EP2C50F672C8
✅ Drop-In✓ In Stock
$155.4 / Unit
View Datasheet →EP2C70F672C8KK Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Logic Elements (LE) | 68,416 |
| Embedded Memory (Bits) | 1,152,000 (4,225 Kbits) |
| Embedded 18x18 Multipliers | 150 |
| Maximum User I/O | 422 |
| PLLs | 4 |
| Global Clock Networks | 16 |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm |
| Maximum Internal Frequency | 402.58 MHz |
| Speed Grade | 8 (C8) |
| Package | 672-pin FBGA |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0C to +85C (commercial) |
| Configuration Method | Active Serial (AS), Passive Serial (PS), JTAG |
| RoHS Status | Compliant |
EP2C70F672C8KK 672-pin fbga Pin Configuration Guide
Pin configuration for EP2C70F672C8KK (672-pin fbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C70F672C8KK.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C70F672C8KK is suitable for 6 applications: Video Surveillance and Image Processing, Industrial Motor Control, Software-Defined Radio Front-End, Automotive Infotainment Prototype, Embedded Control Plane for Networking, Test and Measurement Instrumentation.
Video Surveillance and Image Processing
The EP2C70F672C8KK is well-suited for video surveillance pipelines because its 68,416 logic elements and 150 embedded 18x18 multipliers support real-time pixel-level DSP such as 2D FIR filtering, motion estimation, and edge detection. The 1,152 Kbits of M9K block RAM serve as line buffers for D1 through 720p video at 60 fps without external memory pressure. With 422 user I/O, the device accepts parallel BT.656, BT.1120, or LVDS camera inputs directly, and PLLs generate the pixel clocks needed for synchronous capture. This makes the EP2C70F672C8KK a common choice for legacy multi-channel DVR designs where Cyclone II is qualified and proven in the field.
Recommended
Industrial Motor Control
Industrial motor drives benefit from the EP2C70F672C8KK's combination of fast logic throughput, ample block RAM, and four PLLs for precise PWM generation. The 150 DSP multipliers accelerate field-oriented control (FOC) algorithms, including Clarke/Park transforms and PI controllers running at 20-40 kHz loop rates. The 422 user I/O can interface to multi-axis encoder inputs (QEP, SSI, EnDat) and gate-driver PWM outputs simultaneously. Commercial-grade 0C to +85C operation matches typical industrial cabinet thermal envelopes. For new industrial designs, however, engineers should evaluate Cyclone IV E or MAX 10 since Cyclone II is NRND.
Recommended
Software-Defined Radio Front-End
Software-defined radio (SDR) systems up to several tens of MHz of bandwidth can be hosted on the EP2C70F672C8KK. The 18x18 multipliers implement digital down-conversion (DDC) chains, FIR decimation filters, and FFT bins for spectrum analysis. LVDS I/O pairs handle high-speed ADC/DAC data capture at up to several hundred Mbps, while four PLLs synthesize the ADC sampling clocks and baseband DSP clock from a single reference oscillator. The 1.2 V core and adjustable per-bank VCCIO allow direct interfacing to common ADC interfaces like the AD9228 family without level shifters.
Recommended
Automotive Infotainment Prototype
Although the EP2C70F672C8KK is commercial grade (0C to +85C) rather than AEC-Q100 qualified, it has been widely used in pre-production automotive infotainment and driver-information prototypes. Its 68,416 LEs are sufficient to drive LCD panels, decode compressed audio (MP3, AAC), and handle CAN/LIN bus bridging in parallel. The 422 user I/O easily supports composite video, RGB LCD, and capacitive touch interfaces. Note that for production automotive designs, engineers must migrate to AEC-Q100-qualified Cyclone IV E or MAX 10 devices - the EP2C70F672C8KK is not suitable for AEC-Q100 production deployment.
Recommended
Embedded Control Plane for Networking
Legacy networking equipment uses the EP2C70F672C8KK as a control-plane processor for low-latency packet classification, queue management, and traffic shaping. The 16 global clock networks and four PLLs handle multiple Ethernet PHYs at 10/100/1000 Mbps, while the 150 multipliers accelerate hash-table lookups and CRC calculations. Block RAM stores routing tables and packet descriptors in on-chip memory, eliminating external SRAM access in the hot path. The 672-BGA package's controlled-impedance routing supports RGMII and SGMII interfaces cleanly on a 6-8 layer PCB.
Recommended
Test and Measurement Instrumentation
Test equipment manufacturers have used the EP2C70F672C8KK to build digital storage oscilloscopes, logic analyzers, and protocol analyzers in the 100-500 MHz bandwidth range. The device's 422 user I/O support high-channel-count logic capture or stimulus generation, while the 150 DSP multipliers enable FFT-based spectrum analysis and digital filtering. The four PLLs synthesize multiple synchronized sample clocks for time-interleaved ADCs. The M9K block RAM stores acquisition buffers, reducing the depth of external DDR memory required. Combined with JTAG-based debug, this makes the EP2C70F672C8KK a flexible platform for mid-range T&M products.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C8KK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C8 | EP2C70F672C7N | EP2C70F672C6N | EP2C50F672C8 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 672-FBGA (F672) | 672-FBGA (F672) - same | 672-FBGA (F672) - same | 672-FBGA (F672) - same | 672-FBGA (F672) - same |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 50,316 (-27%) |
| Speed Grade | C8 | C8 | C7 (faster) | C6 (fastest) | C8 |
| Embedded Memory (Kbits) | 1,152 | 1,152 | 1,152 | 1,152 | 594 (-48%) |
| Embedded 18x18 Multipliers | 150 | 150 | 150 | 150 | 86 (-43%) |
| Maximum User I/O | 422 | 422 | 422 | 422 | 422 (same package) |
| PLLs | 4 | 4 | 4 | 4 | 4 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest-density Cyclone II in 672-BGA package (vs EP2C50F672C8)
- C8 speed grade offers broadest third-party tooling compatibility (vs EP2C70F672C7N)
- KK ordering suffix documents full RoHS / lead-free compliance (vs EP2C70F672C8 (without KK suffix))
Design Notes
The Cyclone II EP2C70 requires a multi-rail power tree: 1.2 V core (VCCINT), 2.5 V PLL analog supply (VCCA_PLL), and per-bank I/O supplies (VCCIO). Each VCCIO bank can operate at 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V to match the connected device. Decoupling requires 0.1 uF X7R ceramic capacitors within 100 mils of every VCCINT/VCCIO pin plus bulk 47-100 uF tantalum or polymer capacitors at the regulator outputs. Power sequencing should bring up VCCINT before VCCIO to avoid latch-up; many Cyclone II designs use a sequenced controller like the LTC2974.
The 672-ball FBGA at 1.0 mm pitch requires a minimum of 6 PCB layers with microvia (laser-drilled) stack-ups. Signal breakout uses dog-bone or via-in-pad fanout, with the inner layer dedicated to a solid ground plane adjacent to the BGA for return-path integrity. Matched-length routing is critical for LVDS pairs - keep length mismatch under 100 mil and maintain 100 ohm differential impedance. Use at least 4 signal layers to break out the 422 user I/O plus clock pairs cleanly.
Estimated: junction temperature for a fully-utilized EP2C70 at typical 60-70% toggle rate is approximately 12-18W. Without thermal management via 4-layer PCB copper pours and adequate airflow, junction temperature can exceed the commercial 85C limit. Always enable the on-chip Temperature Sensing Diode and monitor via JTAG during qualification. Also verify that the configuration scheme (AS vs PS) matches the selected boot flash (EPCS family supports AS; older EPCS4 may not have sufficient capacity for EP2C70 bitstreams - use EPCS16 minimum, EPCS64 preferred).
Compliance Information
KK ordering suffix denotes RoHS / lead-free variant per Altera legacy ordering codes. Commercial temperature grade 0C to +85C. Not AEC-Q100 qualified - choose Cyclone IV E automotive grade for AEC-Q100 needs.
