EP2C70F672C8 - Cyclone II FPGA 70K LE 672-BGA | Intel
MPN: EP2C70F672C8 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $321.56 | $321.56 |
| 10 | $305.5 | $3,055.00 |
| 100 | $285.4 | $28,540.00 |
| 500 | $261.75 | $130,875.00 |
| 1,000 | $238.2 | $238,200.00 |
EP2C70F672C8 Overview
A Field Programmable Gate Array (FPGA) is a programmable logic device whose logic, routing, and I/O behaviour are defined by configuration bitstream rather than by mask-level silicon fabrication. FPGAs sit above CPLDs in the programmable logic hierarchy, and below ASICs in unit cost but above them in design flexibility. Cyclone II specifically targets the low-power, low-cost end of the FPGA market and is widely used for parallel I/O expansion, glue logic, video bridging, and DSP pre-processing.
Key features of the EP2C70F672C8 include 68,416 logic elements, 250 MHz maximum operating frequency, 1,152,000 bits of embedded RAM arranged in M4K blocks, 150 embedded 18x18 multipliers, up to 422 user I/O pins with support for multiple I/O standards (LVDS, LVTTL, LVCMOS, SSTL, PCI, PCI-X), and four phase-locked loops (PLLs) for clock management. The 672-BGA FineLine package provides a high pin density that supports the largest Cyclone II member in this family.
The Cyclone II architecture uses 4-input look-up tables (LUTs), embedded memory blocks, and dedicated multiplier blocks for DSP arithmetic. The 90 nm process delivers an optimal balance of cost, density, and static power consumption. Configuration bitstreams are loaded via JTAG, Active Serial (AS), or Passive Serial (PS) modes, with optional decompression and Cyclic Redundancy Check (CRC) verification.
Typical applications include industrial motor control, video surveillance systems, automotive infotainment pre-processing, flat-panel display controllers, and telecom line cards. The combination of high logic density and embedded multipliers also enables soft-core processor implementations (e.g., Nios II) for embedded control.
When designing with the EP2C70F672C8, ensure adequate decoupling and consider thermal management through PCB copper pours. Designers should use Quartus II development software for synthesis, place-and-route, and timing closure; legacy Cyclone II designs should migrate to Cyclone IV or Cyclone V devices for new projects.
This page synthesizes distributor pricing, verified drop-in alternatives from the Cyclone II family, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2C70F672C8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2C70F672C8 (same form factor and footprint) — differing in Package, Speed Grade, RoHS Status, Family, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2C70F672C8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$239.75 / Unit
View Datasheet →EP2C70F672C7
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$278 / Unit
View Datasheet →EP2C70F672C7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C6
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$338.91 / Unit
View Datasheet →EP2C70F672C6N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$178.3 / Unit
View Datasheet →EP2C70F672I7N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP2C70F672I8N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$195 / Unit
View Datasheet →EP2C70F672C8 Maximum Ratings & Electrical Characteristics
| Family | Cyclone II |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements | 68,416 |
| Total RAM Bits | 1,152,000 |
| Number of I/O | 422 |
| Number of LABs/CLBs | 4276 |
| Embedded Multipliers (18x18) | 150 |
| Number of PLLs | 4 |
| Maximum Operating Frequency | 250 MHz |
| Process Technology | 90 nm CMOS |
| Package Type | 672-BGA FineLine (FBGA-672) |
| Package Dimensions | 27 mm x 27 mm |
| Operating Temperature Range | 0C to +85C (Commercial, 'C' suffix) |
| Speed Grade | 8 |
| Configuration Mode | AS / PS / JTAG |
| I/O Standards Supported | LVDS, LVTTL, LVCMOS, SSTL, PCI, PCI-X |
| RoHS Status | Compliant |
EP2C70F672C8 27 mm x 27 mm Pin Configuration Guide
Pin configuration for EP2C70F672C8 (27 mm x 27 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2C70F672C8.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2C70F672C8 is suitable for 6 applications: Industrial Motor Control and Drive, Video Surveillance and Image Processing, Flat-Panel Display Controller and TCON, Telecom Line Card and Protocol Bridging, Automotive Infotainment Pre-Processing, Soft-Core Processor Embedded System (Nios II).
Industrial Motor Control and Drive
The EP2C70F672C8 is well-suited for industrial motor control applications because its 150 embedded 18x18 multipliers and 250 MHz maximum operating frequency enable simultaneous field-oriented control (FOC) loops on multi-axis drives. The 422 user I/O pins accommodate quadrature encoder inputs, PWM outputs, resolver feedback, and CAN/RS-485 communications without external bus expanders. The 90 nm Cyclone II silicon provides deterministic latency for safety-critical control loops, while 1,152,000 bits of embedded RAM buffer sensor data and reference trajectories. PCB layout benefits from the 672-FBGA package's 1.0 mm pitch fan-out, allowing compact drive boards that fit standard 100 mm x 150 mm form factors common in industrial servo products.
Recommended
Video Surveillance and Image Processing
The EP2C70F672C8 supports multi-channel video surveillance designs where its 68,416 logic elements can implement parallel pixel-processing pipelines for H.264 encoding, motion detection, and overlay compositing on D1/720p streams. The 1,152,000 bits of embedded RAM act as line buffers and frame-storage for temporal noise reduction, while 422 I/O pins connect to multiple CMOS sensors, BT.656 video ADCs, and DDR memory for frame buffering. The 672-FBGA package's high pin count lets designers integrate 4-8 video input channels without external muxing. Quartus II synthesis libraries include optimised video IP cores that map efficiently to Cyclone II DSP blocks and M4K memory.
Recommended
Flat-Panel Display Controller and TCON
In flat-panel display timing-controller (TCON) applications, the EP2C70F672C8's 250 MHz fabric speed supports WUXGA (1920x1200) and 4K2K input timing with LVDS and mini-LVDS panel interfaces. The 150 embedded 18x18 multipliers handle pixel-format conversion, gamma correction, and overdrive calculations across multiple display layers. The 672-FBGA FineLine package exposes enough I/O for 8-lane mini-LVDS, 4-channel LVDS input, and side-band control signals to the panel and backlight driver. Embedded M4K RAM blocks hold gamma lookup tables and frame-rate-conversion buffers without consuming logic elements, leaving more LE budget for image-enhancement algorithms.
Recommended
Telecom Line Card and Protocol Bridging
The EP2C70F672C8 is appropriate for telecom line cards performing TDM-to-Ethernet protocol bridging, framer aggregation, and HDLC encapsulation where deterministic latency and high logic density are required. The four PLLs generate multiple clock domains for E1/T1, STM-1, and gigabit Ethernet interfaces simultaneously without external clock generators. 422 user I/O pins handle 8-16 TDM timeslots, SPI/I2C control buses, and management interfaces. The 1,152,000 bits of embedded RAM implement per-channel FIFOs that absorb jitter across asynchronous clock domains. Cyclone II's 90 nm process delivers predictable timing closure for telecom-grade designs.
Recommended
Automotive Infotainment Pre-Processing
Although the EP2C70F672C8 itself is commercial-temperature, designers building pre-production automotive infotainment prototypes use it for fast HDL iteration before migrating to industrial-temperature EP2C70F672I8N drop-in equivalents. The 68,416 logic elements implement multiple video pipeline stages: image scaling, color-space conversion, and alpha blending for head-unit displays. The 150 embedded multipliers accelerate de-interlacing and noise reduction on composite video inputs from rear-view cameras. 422 user I/O pins accommodate CAN, LIN, MOST, and LVDS display interfaces common in automotive infotainment architectures. Designers retain the option to switch to the I-grade variant for production deployment without any PCB change.
Recommended
Soft-Core Processor Embedded System (Nios II)
The EP2C70F672C8 is an ideal host for Nios II soft-core processors in embedded applications because 68,416 logic elements accommodate a 32-bit Nios II/f core with MMU, instruction and data caches, and multiple peripherals such as Ethernet MAC, USB device, and DDR controller. The 1,152,000 bits of embedded RAM provide tightly-coupled memory regions for deterministic interrupt latency, while 422 user I/O pins expose the full set of Altera Avalon peripherals including SPI, I2C, UART, and GPIO. The 672-FBGA package supports a 32-bit DDR memory data bus plus address and control signals without bus muxing. Designers building Nios II systems benefit from Quartus II SOPC Builder integration and the Cyclone II reference designs for Ethernet and USB.
Recommended
Recommended Products Summary
Engineering reference data for EP2C70F672C8 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2C70F672C8N | EP2C70F672C7 | EP2C70F672C7N | EP2C70F672C6 | EP2C70F672C6N | EP2C70F672I7N | EP2C70F672I8N |
|---|---|---|---|---|---|---|---|---|
| Package | 672-BGA FineLine (FBGA-672, 27x27 mm) | 672-BGA FineLine - same | 672-BGA FineLine - same | 672-BGA FineLine - same | 672-BGA FineLine - same | 672-BGA FineLine - same | 672-BGA FineLine - same | 672-BGA FineLine - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 | 68,416 |
| Speed Grade | 8 | 8 | 7 | 7 | 6 (fastest) | 6 (fastest) | 7 | 8 |
| Operating Temperature Range | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| Lead-Free (Pb-Free) | No (SnPb finish) | Yes (N suffix) | No | Yes | No | Yes | Yes | Yes |
| Embedded RAM Bits | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 | 1,152,000 |
| Maximum User I/O | 422 | 422 | 422 | 422 | 422 | 422 | 422 | 422 |
| Embedded Multipliers (18x18) | 150 | 150 | 150 | 150 | 150 | 150 | 150 | 150 |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
Key Differentiators
- Speed grade 8 offers cost advantage over speed-grade-6 variants (vs EP2C70F672C6)
- Commercial temperature vs industrial temperature drop-in option (vs EP2C70F672I8N)
- Last-time-buy status - inventory still available vs newer families (vs Cyclone IV EP4CE70F29)
- Largest Cyclone II member with maximum density and I/O (vs EP2C35F672C8N)
Design Notes
The 672-FBGA package uses 1.0 mm ball pitch with a 27 mm x 27 mm body. PCB fabrication must support laser-drilled micro-vias or stacked-via build-up; standard 0.4 mm-pitch BGA rules apply. Place at least four PCB layers (signal, GND, power, signal) under the BGA with continuous GND plane for return-path integrity. All decoupling capacitors (0.1 uF, 0.01 uF) must be placed within 5 mm of their respective VCC pins; an additional 10 uF bulk capacitor per VCC rail is recommended.
Estimated: with 422 I/O toggling at 100 MHz, the EP2C70F672C8 can dissipate up to 2-3 W depending on toggle rate and utilization. With a 672-FBGA junction-to-ambient theta_JA of approximately 15 C/W on a JEDEC 4-layer test board, junction temperature rises 30-45 C above ambient at typical usage. For high-utilization designs, design the PCB with copper pours on all inner layers connected to GND and via-fenced thermal pads. Do not assume the FBGA package can rely on convection alone without a thermal via array under the centre balls.
Cyclone II configuration requires correct MSEL pin settings for AS (Active Serial), PS (Passive Serial), or JTAG modes; incorrect MSEL prevents the FPGA from configuring. JTAG chain integrity must be verified with the Quartus II programmer before attaching signal sources. Unused I/O pins default to tri-stated but can be set to weak pull-up in Quartus II assignments; never leave I/O pins floating if the design drives external buses. Bank VCCIO voltages must match the I/O standard selected (e.g., 3.3 V for LVTTL/LVCMOS, 2.5 V for SSTL-II).
Differential pair routing (LVDS) on Cyclone II requires matched-length matching to within 150 mil for data rates up to 640 Mbps. Use 100 ohm differential impedance for LVDS pairs and 50 ohm single-ended for CMOS standards. Place clock inputs on dedicated clock pins (CLK[0..15]) routed with controlled impedance and length matching to within 50 mil of source. JTAG signals TCK, TMS, TDI, TDO should be guarded by GND traces and pulled to known states via 10 kohm resistors as recommended in the Cyclone II handbook.
Compliance Information
EP2C70F672C8 has no N-suffix, indicating SnPb (leaded) finish. Lead-free equivalent is EP2C70F672C8N. RoHS/REACH/AEC-Q100 status not explicitly provided in the verified distributor web data - marked unknown. Industrial-grade variants (EP2C70F672I7N, EP2C70F672I8N) are available for extended temperature requirements but are not AEC-Q100 qualified for automotive safety applications.
