EP2S60F672I5 - 60K LEs Stratix II FPGA, 672-FBGA | Intel / Altera
MPN: EP2S60F672I5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1690 | $16,900.00 |
| 100 | $1520 | $152,000.00 |
| 500 | $1380 | $690,000.00 |
| 1,000 | $1245 | $1,245,000.00 |
EP2S60F672I5 Overview
A Field-Programmable Gate Array (FPGA) is a semiconductor device whose digital logic and routing are defined by a user-supplied configuration bitstream rather than at the factory. Within the broader taxonomy of programmable logic devices (PLDs), FPGAs sit above simple CPLDs and below structured ASICs in cost-per-volume but far above both in design flexibility. FPGAs are used to implement arbitrary digital functions - from glue logic and bus interfaces to entire SoC prototypes - while preserving the ability to re-spin the design in minutes. The Stratix II family targets high-performance compute, communication, and signal-processing applications where high logic density, large block memory, and abundant DSP throughput are required.
Key features of the EP2S60F672I5 include 60,440 logic elements (LEs), 36 DSP blocks equivalent to 288 18x18 multipliers, 12 PLLs with on-chip termination support, and 2,544,192 RAM bits distributed across M4K and M-RAM memory blocks. The device also exposes 12 transceiver channels on selected package variants, though the F672 ball-out does not break out transceivers. Configuration is supported via passive serial (PS), fast passive parallel (FPP), and JTAG modes, with optional configuration via EPC16 or EPCS serial configuration devices.
At the architecture level, the Stratix II device uses adaptive logic modules (ALMs) - an 8-input fracturable LUT that can implement either a full 6-input LUT or two smaller LUTs sharing common inputs - paired with TriMatrix memory blocks (MLAB, M4K, M-RAM) and dedicated high-speed I/O serdes on supported packages. The 'I5' speed grade corresponds to a -5 speed bin, while the trailing 'I' denotes the industrial temperature range (-40C to +100C junction). Power estimation tools such as the Altera PowerPlay Early Power Estimator and TimeQuest timing closure are required to validate thermal and timing budgets at 1.2 V core.
Typical applications include high-speed digital signal processing (radar, baseband, software-defined radio), ASIC prototyping and emulation, high-throughput data acquisition and aggregation, video and image processing pipelines, and high-speed serial protocol bridging (PCI Express, Serial RapidIO, Gigabit Ethernet). The combination of 60K LEs and 36 DSP blocks makes the EP2S60 well-suited to multi-channel DSP designs that would otherwise require multiple smaller FPGAs.
When designing with this part, use the Quartus II design software (version 9.0 or later) and verify that the selected pin-out F672 matches your board's BGA footprint. Industrial temperature operation requires a junction-to-ambient thermal analysis; the 672-ball FC-FBGA has a theta-JA of approximately 9.1 C/W with appropriate heatsinking, and worst-case core power can exceed 10 W.
This page synthesizes distributor pricing, drop-in alternatives, and practical Stratix II design notes not always found in a single manufacturer document.
Drop-in alternatives for EP2S60F672I5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672I5 (same form factor and footprint) — differing in Package, Speed Grade, RoHS Status, Core Voltage, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S60F672I4
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1050 / Unit
View Datasheet →EP2S60F672I4N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$220 / Unit
View Datasheet →EP2S60F672C5
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$410.85 / Unit
View Datasheet →EP2S60F672C4
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1080 / Unit
View Datasheet →EP2S60F672C3
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1033.14 / Unit
View Datasheet →EP2S60F672I5 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 60,440 |
| Adaptive Logic Modules (ALMs) | 24,176 |
| Embedded RAM Bits | 2,544,192 |
| DSP Blocks | 36 |
| 18x18 Multipliers | 144 |
| PLLs | 12 |
| Maximum User I/O | 492 |
| Package | 672-ball FC-FBGA (F672) |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V |
| Speed Grade | -5 (I5) |
| Operating Temperature | -40C to +100C (industrial) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
EP2S60F672I5 672-ball fc-fbga (f672) Pin Configuration Guide
Pin configuration for EP2S60F672I5 (672-ball fc-fbga (f672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S60F672I5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S60F672I5 is suitable for 6 applications: High-Speed Digital Signal Processing, ASIC Prototyping and Emulation, High-Speed Serial Protocol Bridging, Video and Image Processing, Industrial Control and Test Equipment, Telecom Baseband Processing.
High-Speed Digital Signal Processing
The EP2S60F672I5's 36 DSP blocks (144 18x18 multipliers) and 60,440 logic elements make it a strong fit for multi-channel DSP pipelines such as radar baseband, software-defined radio (SDR) front-ends, and beamforming arrays. At 1.2 V core and speed grade -5, the device sustains 250+ MHz FIR filter throughput per multiplier chain. Designers typically pair the S60 with external DDR2 SDRAM via the dedicated DQS pins for sample buffering. The industrial temperature range allows deployment in outdoor or ruggedized enclosures without thermal derating.
Recommended
ASIC Prototyping and Emulation
The 60K-LE capacity of the EP2S60F672I5 is well suited to ASIC prototyping of mid-complexity SoCs (up to ~2 M gates when mapped 1:3). Multiple EP2S60 devices can be tiled on a prototyping board to emulate larger designs, with the Quartus II multi-device partition flow handling time-budgeting across chips. The 492 user I/Os expose enough pins to break out most ASIC peripheral interfaces, and the 12 PLLs provide flexible clock domain generation for emulating mixed-speed SoC clocks.
Recommended
High-Speed Serial Protocol Bridging
The Stratix II architecture supports dedicated high-speed serial I/O up to 1 Gbps on selected package variants, making the EP2S60F672I5 useful for bridging between PCI Express, Serial RapidIO, and Gigabit Ethernet domains. The 12 PLLs and abundant ALM-based logic enable complex PCS and MAC layers alongside the SERDES channels. Industrial temperature operation permits deployment in telecom and industrial networking equipment that must operate continuously outside air-conditioned environments.
Recommended
Video and Image Processing
The 2,544,192 bits of embedded RAM, distributed across M4K and M-RAM blocks, give the EP2S60F672I5 enough on-chip buffering to hold several lines of HD video for real-time image processing pipelines such as motion estimation, color space conversion, and edge detection. The 36 DSP blocks accelerate convolution and DCT operations at video rates, while the 492 user I/Os can drive multiple DVI/HDMI output channels or camera input ports directly. Industrial temperature is acceptable for broadcast and surveillance outdoor installations.
Recommended
Industrial Control and Test Equipment
The EP2S60F672I5 is widely deployed in high-end industrial test and measurement platforms, where its combination of 60K LEs, 12 PLLs, and 492 I/Os can replace multiple discrete microcontrollers and DSPs in a single device. The industrial temperature range (-40C to +100C junction) and 90 nm process reliability support long-life industrial deployments. The BGA package withstands vibration when properly socketed, and the device's deterministic latency makes it suitable for closed-loop control and protocol-aware test equipment.
Recommended
Telecom Baseband Processing
The EP2S60F672I5 has been used in 3G/4G baseband processing cards, where its 36 DSP blocks accelerate channel estimation, FFT/iFFT, and turbo decoding, and its 60,440 LEs implement MAC-layer scheduling and backhaul interfaces. The 12 PLLs provide the multiple reference frequencies required for mixed sample-rate chains, and the 1.2 V core with industrial temperature suits outdoor base station enclosures. The F672 BGA footprint has been adopted as a de-facto standard across several telecom OEM reference designs.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672I5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672I4 | EP2S60F672I4N | EP2S60F672C5 | EP2S60F672C4 | EP2S60F672C3 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FC-FBGA (F672) | 672-ball FC-FBGA (F672) - same | 672-ball FC-FBGA (F672) - same | 672-ball FC-FBGA (F672) - same | 672-ball FC-FBGA (F672) - same | 672-ball FC-FBGA (F672) - same |
| Logic Elements | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | -5 (fastest) | -4 | -4 | -5 | -4 | -3 (slowest) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty 1) | USD 1,850 | USD 1,500-1,700 | USD 1,500-1,700 | USD 1,400-1,600 | USD 1,200-1,400 | USD 1,000-1,200 |
Key Differentiators
- Fastest speed grade at industrial temperature in the F672 ball-out (vs EP2S60F672I4)
- Industrial temperature range (vs commercial C-grade) (vs EP2S60F672C5)
- Same F672 BGA footprint across entire EP2S60 family (vs EP2S60F1020C5)
Design Notes
The EP2S60F672I5 in the 672-ball FC-FBGA can dissipate 8-15 W in DSP-heavy designs. The 672-ball package has a theta-JA of approximately 9.1 C/W with a 1 oz copper inner layer and 200 LFM airflow, per the Altera Stratix II Packaging Guidelines. Industrial-temperature operation requires the junction to stay below 100C; derate the design margin accordingly when using PowerPlay Early Power Estimator results.
The 1.0 mm pitch FC-FBGA requires microvia or via-in-pad PCB technology for reliable assembly. Land pattern and solder ball geometry must follow the Altera-recommended 0.6 mm diameter solder mask defined pads. MSL3 moisture handling is mandatory because plastic BGA packages absorb moisture and can crack during reflow. Stencil design for BGA rework should use a laser-cut stencil with 0.005 inch thickness for production volumes.
Stratix II is in obsolete lifecycle status as of the latest Intel product change notifications. Do not design the EP2S60F672I5 into new production programs without a documented migration path (Stratix IV EP4SGX230 or Cyclone V GX are the typical successors). For long-life industrial programs, qualify a broker with full traceability and ESD/inspection records, or plan a board redesign to a current device immediately. Quartus II version 9.0 or later is required for synthesis; the legacy Web Edition is no longer downloadable from Intel.
The high-density 492-I/O interface on the 672-ball BGA includes 8-12 dedicated global clock networks and 12 PLLs. Source-synchronous DDR/DDR2 interfaces (up to 333 MHz) require matched-length fly-by routing with the DQS pins centered on the byte group. Use the TimeQuest timing analyzer within Quartus II to close timing on memory interfaces, and verify SI with HyperLynx or ANSYS SIwave for production sign-off.
Compliance Information
RoHS compliance per Altera/Intel product page; not AEC-Q100 qualified (FPGA, not a discrete automotive IC). Halogen-free status not explicitly confirmed in verified web data.
