EP2S90F1508C4N - 90K LE Stratix II FPGA, 902 I/O, 1508-BGA | Intel
MPN: EP2S90F1508C4N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1836 | $1,836.00 |
| 5 | $1740 | $8,700.00 |
| 10 | $1655 | $16,550.00 |
| 25 | $1525 | $38,125.00 |
| 100 | $1390 | $139,000.00 |
EP2S90F1508C4N Overview
An FPGA (Field Programmable Gate Array) is a semiconductor device containing programmable logic blocks, interconnect, and I/O cells that can be configured post-manufacture to implement arbitrary digital circuits. Stratix II belongs to the high-performance FPGA family tier, sitting above Cyclone (cost-optimized) and below Stratix GX/GT (transceiver-equipped) variants. FPGAs occupy the same broad product category as ASICs, CPLDs, and microcontrollers, but offer unique advantages in parallelism, reconfigurability, and time-to-market for DSP, communications, and prototyping workloads.
Key features of the EP2S90F1508C4N include 12 dedicated PLLs (Phase-Locked Loops) for clock synthesis, up to 4 Mb of TriMatrix embedded memory distributed across MRAM, M512, and M4K blocks, dedicated DSP blocks for high-throughput arithmetic, and support for external memory interfaces including DDR, DDR2, SDRAM, QDRII, and RLDRAM II. The device family integrates high-speed serial I/O capability through dedicated DPA circuitry, and supports LVDS, LVPECL, and HSTL I/O standards with user-selectable drive strength from 2 mA to 24 mA.
The architecture combines Adaptive Logic Modules (ALMs) - each containing two 4-input LUTs, two programmable registers, and dedicated adder circuitry - with MultiTrack interconnect that delivers predictable timing closure at 90 nm node performance targets. Embedded memory blocks support true dual-port operation and mixed-width data paths, while DSP blocks deliver up to 36 x 36 bit multiplies per block at full pipeline speed.
Typical applications include high-speed digital signal processing (radar, beamforming, software-defined radio), ASIC prototyping, telecommunications infrastructure (SONET/SDH, OTN framers), high-performance computing accelerators, video processing pipelines, and military/aerospace embedded systems. Designers select this part when logic density above 70K LEs is required together with abundant embedded memory and DSP resources in a single device.
When designing with this device, pay close attention to power supply decoupling (a Stratix II FPGA typically requires multiple 1.2 V, 2.5 V, and 3.3 V rails with strict sequencing requirements), thermal management (the 1508-ball FCBGA exposes a thermal pad that must be soldered to a properly sized PCB copper pour), and signal integrity on 902 simultaneously-switching outputs (SSO analysis is mandatory). Quartus II is the supported design toolchain.
This page synthesizes distributor pricing, drop-in same-package alternatives within the Stratix II family, and practical design notes not found in the manufacturer datasheet - giving engineers a faster sourcing and evaluation workflow.
Drop-in alternatives for EP2S90F1508C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1508C4N (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature Grade, Configuration Method, Logic Array Blocks (LABs).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90F1508C4
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2S90F1508C3N
β Drop-Inβ In Stock
$3200 / Unit
View Datasheet βEP2S90F1508C5N
β Drop-Inβ In Stock
$3780 / Unit
View Datasheet βEP2S130F1508C4N
β Drop-Inβ In Stock
$4435.83 / Unit
View Datasheet βEP2S180F1508C4N
β Drop-Inβ In Stock
$985 / Unit
View Datasheet βEP2S180F1508C3N
β Drop-Inβ In Stock
$1200 / Unit
View Datasheet βEP2S90F1508C4N Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Logic Array Blocks (LABs) | 4548 |
| Embedded Memory Bits | 4,520,488 |
| Maximum User I/O | 902 |
| PLLs (Phase-Locked Loops) | 12 |
| Core Voltage | 1.2 V |
| Maximum Internal Frequency | 711.24 MHz |
| Process Technology | 90 nm CMOS |
| Package | 1508-Ball FC-FBGA (Flip-Chip BGA) |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature Grade | Commercial (0C to +85C) |
| Speed Grade | C4 |
| Configuration Method | Serial / Passive Parallel / Fast Passive Parallel |
EP2S90F1508C4N 1508-ball fc-fbga (flip-chip bga) Pin Configuration Guide
Pin configuration for EP2S90F1508C4N (1508-ball fc-fbga (flip-chip bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1508C4N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1508C4N is suitable for 6 applications: Telecom Infrastructure - SONET/SDH Framer, Software-Defined Radio (SDR) Baseband, ASIC Prototyping and Emulation, High-Performance DSP - Radar Beamforming, Medical Imaging Accelerator (CT/MRI), Video Processing Pipeline (4K Broadcast).
Telecom Infrastructure - SONET/SDH Framer
The EP2S90F1508C4N's 90,960 logic elements, 12 PLLs, and 902 user I/O pins make it well suited for SONET/SDH and OTN framer applications where multi-channel serial links and clock recovery are essential. The 711.24 MHz internal fMAX supports OC-192/STM-64 (9.953 Gbps) line-rate processing when combined with external SERDES, while the abundant TriMatrix memory (4.52 Mbits) buffers payload data across multiple STS/AU containers. Designers place the device between the optical transceiver PHY and a backplane SERDES, with the 1.2 V core drawing typical power in the 5-8 W range depending on toggle rate.
Recommended
Software-Defined Radio (SDR) Baseband
The EP2S90F1508C4N delivers the DSP throughput required for software-defined radio baseband processing, with its dedicated DSP blocks providing 36 x 36 bit multiplies per block at full pipeline speed. The 4.52 Mbit embedded memory buffer stores FFT intermediate samples and channelization tables, while 12 PLLs generate the multiple sample-rate clocks needed for upconversion/downconversion chains. The 902 user I/Os connect to multiple ADC/DAC channels (such as TI ADS62Pxx and DAC38RFxx) for wideband RF sampling architectures spanning VHF to microwave bands.
Recommended
ASIC Prototyping and Emulation
The EP2S90F1508C4N is widely deployed in ASIC prototyping platforms because of its 90,960 logic elements (roughly equivalent to 2-5 million gates of standard-cell ASIC density), abundant I/O for partitioned multi-FPGA emulation, and Quartus II design flow with ASIC-equivalent timing closure. Engineers map target ASICs above ~10 million gates onto multiple Stratix II FPGAs using time-domain or function-domain partitioning, leveraging the 1508-ball FC-FBGA package for high-pin-count chip-to-chip interconnect. Embedded memory supports transaction recording and FIFO buffering between partitioned logic blocks.
Recommended
High-Performance DSP - Radar Beamforming
The EP2S90F1508C4N's parallel DSP architecture is ideal for phased-array radar beamforming and pulse compression, where multiple antenna channels must be processed in real time. Each DSP block can sustain 36 x 36 bit multiplies at full pipeline speed, and the 12 PLLs provide the deterministic clocking required for coherent channel sampling across hundreds of array elements. The 902 user I/Os connect to multi-channel ADC front-ends (such as TI ADC12DJ3200 or AD9680), while 4.52 Mbit embedded memory buffers FFT bins for Doppler processing.
Recommended
Medical Imaging Accelerator (CT/MRI)
The EP2S90F1508C4N suits medical imaging pipelines - CT reconstruction, MRI FFT processing, and ultrasound beamforming - because its parallel DSP blocks deliver the arithmetic throughput required for back-projection, FBP, and 2D/3D FFT kernels. The 4.52 Mbit embedded memory caches sinogram projections and image slices, while the 902 I/Os interface to multi-channel medical imaging sensors and high-speed LVDS data links. Designers use the device to offload reconstruction from the host CPU, achieving real-time image formation with sub-second latency for diagnostic workflows.
Recommended
Video Processing Pipeline (4K Broadcast)
The EP2S90F1508C4N handles real-time 4K video processing for broadcast and Pro-AV applications, leveraging its 902 I/Os to support multiple 3G-SDI or HDMI 2.0 inputs/outputs in parallel. Its 90,960 logic elements implement deinterlacing, scaling, color-space conversion, and frame-rate conversion pipelines without external preprocessing. Embedded TriMatrix memory buffers full 4K frames (3840 x 2160 x 10-bit) for multi-tap filtering, while 12 PLLs synthesize the multiple pixel clocks required by SDI, HDMI, and DisplayPort interfaces.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1508C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1508C4 | EP2S90F1508C3N | EP2S130F1508C4N | EP2S180F1508C4N |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1508-Ball FC-FBGA | 1508-Ball FC-FBGA - same | 1508-Ball FC-FBGA - same | 1508-Ball FC-FBGA - same | 1508-Ball FC-FBGA - same |
| Family | Stratix II | Stratix II - same | Stratix II - same | Stratix II - same | Stratix II - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 132,540 | 179,400 |
| Embedded Memory (bits) | 4,520,488 | 4,520,488 | 4,520,488 | 6,747,840 | 9,383,040 |
| User I/O | 902 | 902 | 902 | 902 | 902 |
| PLLs | 12 | 12 | 12 | 12 | 12 |
| Speed Grade | C4 | C4 | C3 (slower) | C4 | C4 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
Key Differentiators
- Pb-free / lead-free packaging variant of the Stratix II EP2S90F1508C4 (vs EP2S90F1508C4)
- C4 speed grade balances performance and cost (vs EP2S90F1508C3N)
- Logic density option in same package and pinout (vs EP2S130F1508C4N)
Design Notes
The Stratix II EP2S90F1508C4N requires multiple supply rails: VCCINT (1.2 V core), VCCIO (per-bank, typically 1.5 V/1.8 V/2.5 V/3.3 V), VCCAUX (2.5 V), VCCPD (3.3 V), and VCC_CLKIN (2.5 V for PLL clock inputs). Strict power-sequencing is mandatory per the Stratix II PowerPlay user guide - VCCINT must reach its threshold before VCCIO and VCCAUX to prevent latch-up. Use bulk decoupling of at least 100 uF low-ESR electrolytic plus 100 nF ceramic per supply pin, with switching regulator rise times under 100 ms.
Estimated: At typical toggle rate (~30%) the EP2S90F1508C4N dissipates 5-8 W; the 1508-ball FC-FBGA package exposes a central thermal pad that MUST be soldered to a properly designed PCB thermal land. Use a 4-layer minimum PCB with at least 6 square inches of unbroken copper pour tied to the thermal pad, and consider a heat spreader or heatsink for sustained 8 W+ operation. Without thermal pad soldering, junction temperature will exceed the 85 C commercial limit quickly under load.
The 1508-ball FC-FBGA has a fine pitch of 1.0 mm ball spacing - PCB fabrication requires laser-drilled microvias, ENIG surface finish, and 4 mil/4 mil trace/space design rules. Use a fanout pattern with alternating layer via placement, escape routing on inner layers, and ground shielding on signal layers. Length matching must be applied per I/O bank for LVDS and DDR memory interfaces, with impedance control to 50 ohm single-ended or 100 ohm differential per signal-integrity simulations.
Do not mix configuration schemes - the EP2S90F1508C4N supports Fast Passive Parallel (FPP), Passive Serial (PS), and Passive Parallel Asynchronous (PPA) modes selected via MSEL pins, and wiring mistakes cause configuration failure. Verify the JTAG chain IDCODE match before in-system programming. The configuration flash memory interface requires 16-bit data bus; do not connect configuration data bus to user I/O inadvertently. Cyclone III/IV/V boards are NOT pin-compatible with Stratix II.
Compliance Information
RoHS-compliant lead-free packaging (Pb-free suffix 'N'). AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC. Other compliance fields are not explicitly listed in the verified data and remain unknown.
