EP2SGX90EF35C3NES - Stratix II GX 90K LE FPGA, 35-BGA | Intel
MPN: EP2SGX90EF35C3NES β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $145 | $14,500.00 |
| 500 | $128 | $64,000.00 |
| 1,000 | $112 | $112,000.00 |
EP2SGX90EF35C3NES Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and programmable interconnect that the designer programs after manufacture. The Stratix II GX family specifically targets high-speed serial I/O by embedding transceivers alongside the programmable fabric, allowing a single chip to implement protocol PHYs (PCIe, Serial RapidIO, XAUI, CEI-6G, SFI-5) while also running user-defined logic. Within the broader taxonomy, the part sits as: FPGA -> programmable logic device -> logic IC -> integrated circuit -> semiconductor.
Key features include up to 6.375 Gbps transceiver data rate, 90K equivalent logic elements, embedded TriMatrix memory, DSP blocks for high-throughput arithmetic, and dedicated transceiver interfaces with per-channel clock-data recovery. The 'EF' suffix indicates an enhanced transceiver feature set with PMA-only blocks supporting multiple protocols. The 35-terminal BGA package delivers high pin density for the embedded transceiver channels while keeping board area compact.
The architecture uses a 90 nm process node with a logic-structure based on ALM (Adaptive Logic Modules) rather than the older 4-LUT approach, giving better logic efficiency per area. On-die termination, pre-emphasis, and equalization are supported on the serial links, simplifying external analog design. Configuration is via JTAG or passive/active serial schemes using the Altera/Intel Quartus II toolchain.
Typical applications include high-speed serial interface bridging (PCIe Gen1/Gen2, Serial RapidIO, XAUI), telecom backplane aggregation, broadband data aggregation cards, and protocol converter / packet-processing line cards. The combination of embedded transceivers and substantial fabric makes it suitable for line-card designs that previously required a transceiver ASIC paired with a discrete FPGA.
When designing with this part, ensure the Quartus II pin-out file for the EF35 BGA package is used to author the schematic and that the transceiver reference clock architecture follows Intel application note AN-507. Power-rail sequencing must respect the 1.2 V core first, then the 1.5/2.5 V analog supplies, to avoid latch-up.
This page synthesizes distributor pricing, drop-in FPGA alternatives from the same Stratix II GX family, and practical design notes not found in the standalone manufacturer datasheet PDF.
Drop-in alternatives for EP2SGX90EF35C3NES β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90EF35C3NES (same form factor and footprint) β differing in Logic Elements, Package, RoHS Status, Transceiver Channels, Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2SGX90EF35C3N
β Drop-Inπ Reference alternative (not in catalog)
EP2SGX90EF35C4N
β Drop-Inπ Reference alternative (not in catalog)
EP2SGX90EF35C5N
β Drop-Inπ Reference alternative (not in catalog)
EP2SGX90EF35I3N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2SGX90EF35C7N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2SGX130GF40C3NES
β Drop-Inβ In Stock
$124 / Unit
View Datasheet βEP2SGX90EF35C3NES Maximum Ratings & Electrical Characteristics
| Family | Stratix II GX |
| Logic Elements | 90,000 |
| Number of Terminals | 35 |
| Package Type | BGA |
| Package Shape | Square |
| Form of Terminal | Ball |
| Core Supply Voltage | 1.2 V |
| Operating Temperature Grade | Commercial Extended |
| Transceiver Data Rate (max) | 6.375 Gbps |
| Transceiver Channels | 4 to 20 |
| Process Node | 90 nm |
| Logic Element | ALM (Adaptive Logic Module) |
| Configuration Interface | JTAG / Passive Serial / Active Serial |
| Embedded Memory Type | TriMatrix |
EP2SGX90EF35C3NES square Pin Configuration Guide
Pin configuration for EP2SGX90EF35C3NES (square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2SGX90EF35C3NES.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2SGX90EF35C3NES is suitable for 6 applications: PCIe Gen1/Gen2 Endpoint Card, Serial RapidIO Switch Fabric, XAUI / 10G Ethernet Bridge, Telecom Backplane Aggregation, Protocol Converter / Packet Processing, Broadband Access Aggregation Card.
PCIe Gen1/Gen2 Endpoint Card
The EP2SGX90EF35C3NES fits PCIe Gen1/Gen2 endpoint cards because its 6.375 Gbps transceivers comfortably cover the 2.5/5 Gbps PCIe data rate while leaving ample ALM-based fabric for the device-side application logic. Designers instantiate the Altera PCIe hard IP and the on-chip CRU handles 8b/10b encoding, scrambling, and clock recovery without external PHY. The 90K logic elements typically fit a single-function endpoint with DMA engines and modest payload buffering, and the 35-ball BGA is acceptable on a small add-in card.
Recommended
Serial RapidIO Switch Fabric
The EP2SGX90EF35C3NES is well suited to Serial RapidIO (SRIO) switch fabric ports because the transceivers natively support the 1.25/2.5/3.125 Gbps SRIO rates with on-die clock-data recovery. The ALM-based fabric is large enough to implement a multi-port switch controller with packet inspection and congestion management. Using a 35-ball BGA keeps the PHY portion of the board compact while designers route high-speed lanes to the transceiver balls per the Stratix II GX handbook.
Recommended
XAUI / 10G Ethernet Bridge
The EP2SGX90EF35C3NES serves as a XAUI or 10G Ethernet bridge because the transceivers support 3.125 Gbps on each of four lanes to aggregate to the 10 Gbps XAUI rate. The 90K LE fabric implements the XGMII-to-XAUI adaptation plus optional MAC-layer logic for protocol conversion or bridging. Designers use the Altera MAC IP plus XAUI PHY IP and validate signal integrity against IEEE 802.3ae using the Stratix II GX transceiver signal-integrity application notes.
Recommended
Telecom Backplane Aggregation
The EP2SGX90EF35C3NES fits telecom backplane aggregation line cards because its multi-gigabit transceivers can run SFI-5, CEI-6G, or proprietary backplane rates up to 6.375 Gbps with on-chip pre-emphasis and equalization. The 90K LE fabric implements cell/packet aggregation and OAM (Operations, Administration, Maintenance) logic. Designers use the Stratix II GX backplane reference design and Intel application note AN-507 to plan reference-clock architecture and pre-emphasis tap settings.
Recommended
Protocol Converter / Packet Processing
The EP2SGX90EF35C3NES works as a protocol converter or packet-processing engine because the 90K LE fabric and TriMatrix memory block can sustain multi-gigabit packet throughput on-chip while the transceivers connect to multiple front-panel interfaces simultaneously. Typical designs convert between SRIO, XAUI, PCIe, and custom LVDS links. Designers use the Altera packet generator/checker IP plus the SOPC Builder / Qsys interconnect for bus arbitration.
Recommended
Broadband Access Aggregation Card
The EP2SGX90EF35C3NES is suitable for broadband access aggregation cards (DSLAM line cards, PON OLT line cards, DOCSIS upstream aggregation) because the embedded transceivers aggregate multiple SFI/PON lanes while the fabric implements MAC-layer and uplink framing. The 35-ball BGA fits small mezzanine form factors. Designers validate the design against the Altera Triple-Speed Ethernet IP and the Stratix II GX transceiver characterization report for jitter margin.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90EF35C3NES β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90EF35C3N | EP2SGX90EF35C4N | EP2SGX90EF35C5N | EP2SGX90EF35I3N | EP2SGX90EF35C7N | EP2SGX130GF40C3NES |
|---|---|---|---|---|---|---|---|
| Package | BGA-35 | BGA-35 (same) | BGA-35 (same) | BGA-35 (same) | BGA-35 (same) | BGA-35 (same) | BGA-40 (not pin-compatible) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 90,000 | 90,000 | 90,000 | 90,000 | 90,000 | 90,000 | 130,000 (+44%) |
| Speed Grade | C3 | C3 (same) | C4 (slower, -10% Fmax) | C5 (slowest, -20% Fmax) | I3 (industrial temp) | C7 (fastest, +5% Fmax) | C3 (same) |
| Max Transceiver Data Rate | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps |
| Temperature Grade | Commercial Extended | Commercial | Commercial | Commercial | Industrial (-40C to +100C) | Commercial | Commercial Extended |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
Key Differentiators
- Smallest Stratix II GX BGA package for low-cost embedded transceiver designs (vs EP2SGX90EF1152C3N)
- Commercial-extended temperature grade for harsh commercial environments (vs EP2SGX90EF35C3N)
- Higher density upgrade path with same transceiver IP (vs EP2SGX130GF40C3NES)
Design Notes
The Stratix II GX EF35 BGA package is signal-reduced (only 35 balls) so signal escape routing must follow Intel's package ball-out map in the Quartus II pin-out file. High-speed transceiver balls must route with 100-ohm differential impedance and length-matched within the tolerance specified in the Stratix II GX handbook (typically within 150 mil for 5 Gbps lanes). Place the transceiver reference-clock source within 1 inch of the dedicated clock input pins and isolate it from switching digital signals.
Power sequencing must enforce 1.2 V core before the 1.5/2.5 V analog supplies to avoid latch-up of the transceiver I/O. Use a power supervisor with adjustable thresholds (e.g., a TI TPS3808-style monitor) and sequence the analog supplies with a soft-start ramp of at least 1 ms. Decouple each transceiver ball with a 0.1 uF X7R plus a 10 uF X5R bulk cap placed within 100 mil of the supply pin.
Do not confuse the 'EF' transceiver variant with the 'GF' or 'DF' Stratix II GX variants - they support different protocol IP sets. The EF device is PMA-only (physical media attachment), meaning PCIe, XAUI, Serial RapidIO, CEI-6G, and SFI-5 protocols are supported via soft IP plus the PMA, but the device does not include the protocol hard IPs found in 'C' Stratix II GX devices. Always consult the Quartus II device selection guide to confirm IP support before choosing the EF variant.
Compliance Information
RoHS and lead-free status not confirmed in provided web data. Not AEC-Q100 qualified - this is a commercial/industrial FPGA, not an automotive-grade IC.
