EP2SGX90EF35C5NGA - Stratix II GX FPGA 90K LE, 35mm BGA
MPN: EP2SGX90EF35C5NGA ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1720 | $17,200.00 |
| 50 | $1620 | $81,000.00 |
| 100 | $1550 | $155,000.00 |
| 250 | $1490 | $372,500.00 |
EP2SGX90EF35C5NGA Overview
What is a Stratix II GX FPGA? A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnects, and dedicated hard IP such as transceivers, multipliers, and memory blocks. The 'Stratix' family sits in Intel's high-end FPGA portfolio, optimized for performance, density, and high-speed serial I/O. Within the taxonomy: FPGA -> programmable logic device -> ASIC-class reconfigurable logic -> semiconductor. FPGAs are used when time-to-market, hardware reconfigurability, or parallel processing throughput outweigh the per-unit cost advantages of a fixed-function ASIC.
Key features of the EP2SGX90EF35C5NGA include up to 12 full-duplex transceiver channels supporting protocols such as PCI Express Gen1, XAUI, Serial RapidIO, and CEI-6G, 8 PLLs with on-chip termination calibration, and dedicated DSP blocks delivering up to 192 GMACS performance. The 1.2 V core supply with on-chip voltage regulation simplifies power-rail design, while the 1152-pin FineLine BGA (35 mm body) provides a thermally enhanced land pattern with a large exposed die paddle.
Architecturally, the device combines a logic fabric built from adaptive logic modules (ALMs) with hard PCI Express, XAUI, and external memory interface IP, allowing engineers to drop in complete protocol controllers without consuming FPGA fabric. The 90 nm process and 1.2 V core offer a balance of static power and performance for telecom backplane and high-end test equipment applications.
Typical applications include high-end test and measurement instrumentation, telecom backplane aggregation, broadcast video processing, ASIC prototyping, and DSP co-processing cards. The integrated 6.375 Gbps transceivers make the device especially relevant for legacy 10 Gbps Ethernet and RapidIO line-card designs.
When designing with this FPGA, ensure the PCB land pattern matches the 35 mm FineLine BGA recommended by Intel. Thermal management must account for the 1.2 V core current draw at high toggle rates; a minimum 8-layer stack-up with continuous ground and power planes is recommended. The EPC (Enhanced Configuration Device) classification in the part number indicates this device works with the legacy Altera EPC configuration memory family, so the companion configuration PROM must be ordered from the same product tree.
This page synthesizes distributor inventory, Stratix II GX family context, and practical design notes beyond what the manufacturer datasheet alone provides, helping engineers evaluate drop-in variants and long-term supply risk.
Drop-in alternatives for EP2SGX90EF35C5NGA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90EF35C5NGA (same form factor and footprint) — differing in Logic Elements, Package, RoHS Status, Process Technology, Configuration Method.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2SGX90EF35C5NES
✅ Drop-In✓ In Stock
$1285 / Unit
View Datasheet →EP2SGX90EF35C4NGA
✅ Drop-In📋 Reference alternative (not in catalog)
EP2SGX90EF35C3NGA
✅ Drop-In📋 Reference alternative (not in catalog)
EP2SGX90EF35C5NES
✅ Drop-In✓ In Stock
$1285 / Unit
View Datasheet →EP2SGX90EF35C4NES
✅ Drop-In✓ In Stock
$185 / Unit
View Datasheet →EP2SGX90EF35C3NES
✅ Drop-In✓ In Stock
$112 / Unit
View Datasheet →EP2SGX90EF35C5NGA Maximum Ratings & Electrical Characteristics
| Series | Stratix II GX |
| Family Name | Enhanced Configuration (EPC) Device |
| Logic Elements | 90960 (approx.) |
| Embedded Memory | 4.5 Mbits |
| Transceiver Channels | 12 (up to 6.375 Gbps) |
| DSP Blocks | 192 (12x 18x18 multipliers) |
| PLLs | 8 |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm |
| Speed Grade | C5 |
| Package | 1152-pin FineLine BGA (35 mm) |
| Operating Temperature | Commercial (0C to +85C) - inferred from 'C' speed designation |
| RoHS Status | Non-Compliant (per GlobalSpec listing) |
| Configuration | EPC (Enhanced Configuration Device) family |
EP2SGX90EF35C5NGA 1152-pin fineline bga (35 mm) Pin Configuration Guide
Pin configuration for EP2SGX90EF35C5NGA (1152-pin fineline bga (35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2SGX90EF35C5NGA.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2SGX90EF35C5NGA is suitable for 6 applications: Telecom Backplane Aggregation, High-End Test and Measurement Instrumentation, Broadcast Video Processing, ASIC Prototyping, DSP Co-Processing Cards, Legacy Industrial Control and HMI.
Telecom Backplane Aggregation
The EP2SGX90EF35C5NGA's 12 multi-gigabit transceiver channels up to 6.375 Gbps directly support XAUI, Serial RapidIO, and CEI-6G aggregation on telecom line cards. The 90K logic elements handle packet inspection and traffic management fabric, while 4.5 Mbits of embedded RAM buffers cells at line rate. With 192 18x18 multipliers available as DSP blocks, the device performs wire-speed QoS classification and encryption. In a typical deployment, the FPGA sits between a network processor and the backplane SERDES, replacing multiple discrete PHY ICs with a single integrated solution and reducing PCB area by 30-40%.
Recommended
High-End Test and Measurement Instrumentation
The EP2SGX90EF35C5NGA fits the high-throughput signal processing needs of oscilloscope, BERT, and protocol-analyzer platforms. The 192 DSP blocks deliver 192 GMACS for FFT-based spectrum analysis and real-time FIR filtering, while the 12 transceivers accept 6.375 Gbps data streams from high-speed ADCs and DACs without external clock-data-recovery circuitry. Engineers often pair the device with 1 Gsample/s ADC front-ends, using the FPGA to perform real-time triggering and pattern recognition. The 35 mm FineLine BGA's thermally enhanced land pattern supports continuous operation in benchtop instruments with moderate airflow.
Recommended
Broadcast Video Processing
Broadcast video routers and format converters require the EP2SGX90EF35C5NGA's combination of high logic density and multi-gigabit serial I/O for SDI-over-IP and 3G-SDI multiplexing. The 12 transceivers accept SMPTE 424M (3G-SDI) inputs, while the 90K logic elements perform color-space conversion, scaling, and frame-rate adaptation. The 4.5 Mbit embedded RAM acts as a line buffer, eliminating the need for external DDR in some single-stream designs. A typical 16x16 router using one EP2SGX90EF35C5NGA can replace three to four legacy SDI crosspoint ICs.
Recommended
ASIC Prototyping
The EP2SGX90EF35C5NGA serves as a target for ASIC RTL prototyping in the 90K-equivalent-gate range, allowing verification engineers to validate designs at near-ASIC clock rates before tape-out. The 90 nm process and 1.2 V core deliver predictable timing correlation to production ASIC libraries, while the 8 PLLs and 12 transceivers allow designers to prototype SerDes-heavy ASICs with the same silicon used in production. Quartus II's TimeQuest SDC support and the Stratix II GX's rich debug infrastructure (SignalTap II, Logic Analyzer interface) make it a strong choice for hardware/software co-verification.
Recommended
DSP Co-Processing Cards
The EP2SGX90EF35C5NGA's 192 dedicated 18x18 multipliers deliver 192 GMACS of DSP throughput, making it well-suited for radar, sonar, and software-defined-radio co-processing cards. The 12 transceivers accept digitized RF data at up to 6.375 Gbps from high-speed ADCs, while the 90K logic elements implement the surrounding control and DMA fabric. In a typical radar pre-processor, the device performs pulse compression and Doppler filtering directly on the ADC output, reducing host CPU load by 80-90% and enabling real-time situational awareness.
Recommended
Legacy Industrial Control and HMI
Industrial automation platforms integrate the EP2SGX90EF35C5NGA as a high-speed I/O concentrator that aggregates PROFINET, EtherCAT, and CC-Link frames on a single board. The 12 transceivers provide dedicated channels for time-sensitive industrial Ethernet protocols, while the 90K logic elements handle the protocol stacks and motion-control loops. The commercial 0-85C temperature range suits factory-floor enclosure environments with filtered airflow, and the EPC configuration family allows hot-swap firmware updates via standard JTAG.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90EF35C5NGA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90EF35C5N | EP2SGX90EF35C4NGA | EP2SGX90EF35C5NES |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel |
| Package | 1152-pin FineLine BGA (35 mm) | 1152-pin FineLine BGA (35 mm) - same | 1152-pin FineLine BGA (35 mm) - same | 1152-pin FineLine BGA (35 mm) - same |
| Logic Elements | 90960 | 90960 | 90960 | 90960 |
| Speed Grade | C5 (fastest) | C5 | C4 (~10-15% slower Fmax) | C5 |
| Ordering Suffix | NGA (N = lead-free option, GA = JTAG designator) | N (no GA designator) | NGA | NES (extended lead-free) |
| Transceiver Channels | 12 (up to 6.375 Gbps) | 12 (6.375 Gbps) | 12 (6.375 Gbps) | 12 (6.375 Gbps) |
| Embedded Memory | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits | 4.5 Mbits |
| Lifecycle Status | Last-time-buy | Last-time-buy | Last-time-buy | Last-time-buy |
Key Differentiators
- Active commercial production tail through the C5 speed grade (vs EP2SGX90EF35C4NGA)
- Identical silicon, broader ordering code coverage (vs EP2SGX90EF35C5N)
- Lowest-power option within the same F35 footprint (vs EP2SGX90EF35C5NES)
Design Notes
The 1152-pin FineLine BGA (F35) at 1.0 mm ball pitch requires a minimum 8-layer PCB stack-up with 0.5 oz copper on outer layers and 1 oz on inner power/ground planes. Use of a microvia or HDI process is recommended for the BGA break-out; through-via fanout alone is rarely possible at 1.0 mm pitch without signal-integrity loss. Reference the Altera AN 548 pin connection guidelines for the F35 package and validate escape routing with field-solver simulation before tape-out.
Estimated: at full logic utilization (80%) and 100% toggle rate on I/O, the EP2SGX90EF35C5NGA draws approximately 15-20 W from the 1.2 V core rail. With a 35 mm BGA junction-to-ambient thermal resistance (theta_JA) of approximately 8-10 C/W for a 4-layer JEDEC test board, a heatsink is required for continuous operation above 70C ambient. Use a thermal interface material rated for 5-7 C/W or better, and place a thermocouple near the center of the BGA for in-situ monitoring.
Do not apply power to the 1.2 V core rail before the 2.5 V and 3.3 V auxiliary supplies are stable. The Stratix II GX has specific power-sequencing requirements documented in the device handbook; out-of-order ramp can cause long-term reliability degradation or latch-up. Use a power management IC with programmable sequencing or a discrete FET-based sequencer for prototype builds.
Compliance Information
RoHS Non-Compliant per GlobalSpec datasheet listing. Lead-free construction (N suffix). AEC-Q100 not applicable for FPGAs; this is a commercial-temperature device. REACH and conflict-minerals declarations not in the provided data.
