EP2SGX90F1152C3N - 90nm Stratix II GX FPGA, 1152-BGA | Altera
MPN: EP2SGX90F1152C3N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $230 | $23,000.00 |
| 500 | $198 | $99,000.00 |
| 1,000 | $175 | $175,000.00 |
EP2SGX90F1152C3N Overview
What is a Stratix II GX FPGA? The Stratix II GX family is Altera's mid-2000s generation of high-performance, signal-integrity-focused FPGAs built on a 90nm CMOS process with a redesigned adaptive logic module (ALM) architecture. Each ALM contains an 8-input fracturable lookup table (LUT), dedicated registers, and carry-chain logic. The 'GX' suffix denotes integrated multi-gigabit transceivers (MGTs) supporting serializer/deserializer (SerDes) protocols up to 6.375 Gbps. Within the broader taxonomy: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. The Stratix II GX series bridges the gap between the original Stratix GX transceiver devices and later Stratix IV GX designs.
Key features include 4,548 LABs (logic array blocks), 558 user I/O pins, embedded multiplier blocks for DSP, and dedicated high-speed transceivers with embedded 8B/10B encoding. The 1152-BGA package exposes 558 user I/Os while reserving the remaining balls for power, ground, configuration, and high-speed serial links. Tri-matrix memory blocks provide true dual-port RAM, simple dual-port RAM, and FIFO buffers.
Architecturally, the EP2SGX90F1152C3N pairs an ALM-based logic fabric with a structured ASIC-like transceiver and DSP block array, allowing engineers to balance logic, memory, and high-speed serial bandwidth within a single device. The C3 speed grade reflects the slowest of three commercial speed tiers, prioritizing lower dynamic power over maximum Fmax.
Typical applications include 10 Gigabit Ethernet line cards, SONET/SDH framer backplanes, HD-SDI video routing, radar and electronic-warfare DSP pipelines, and high-speed serial protocol bridging. The device is also commonly found in storage-area-network (SAN) controllers and proprietary chip-to-chip backplanes.
Design consideration: the 1152-BGA requires a multi-layer PCB (typically 8 to 12 layers) with controlled-impedance routing for the MGT channels and matched-length differential pairs. Thermal management relies on the package's exposed-die land grid; a heatsink with thermal interface material is typically mandatory at industrial temperatures and full transceiver utilization.
This page synthesizes distributor pricing, FPGA-family pin-compatible drop-in alternatives, and BGA layout guidance beyond what is found in the manufacturer's datasheet.
Drop-in alternatives for EP2SGX90F1152C3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2SGX90F1152C3N (same form factor and footprint) — differing in Speed Grade, Package, Operating Temperature, Total RAM Bits, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2SGX90EF1152C3N
✅ Drop-In✓ In Stock
$1280 / Unit
View Datasheet →EP2SGX90EF1152C4N
✅ Drop-In✓ In Stock
$695 / Unit
View Datasheet →EP2SGX90EF1152C5N
✅ Drop-In✓ In Stock
$1380 / Unit
View Datasheet →EP2SGX90EF1152C4
✅ Drop-In✓ In Stock
$890 / Unit
View Datasheet →EP2SGX90EF1152C3
✅ Drop-In✓ In Stock
$1180 / Unit
View Datasheet →EP2SGX90F1152C3N Maximum Ratings & Electrical Characteristics
| Family | Stratix II GX |
| Logic Elements | 90,960 |
| Adaptive Logic Modules (ALMs) | 45,480 |
| Logic Array Blocks (LABs) | 4,548 |
| Total RAM Bits | 4,520,448 bits |
| Embedded Multipliers (18x18) | 192 |
| User I/O Pins | 558 |
| Multi-Gigabit Transceivers | Up to 12 channels |
| Transceiver Data Rate (max) | 6.375 Gbps |
| Package | 1152-ball FineLine BGA (35 mm x 35 mm) |
| Speed Grade | C3 (commercial slowest) |
| Process Technology | 90 nm CMOS |
| Operating Temperature | 0C to +85C (commercial) |
| Supply Voltage (Core) | 1.2 V |
| Configuration Scheme | Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), JTAG |
| Mounting Type | Surface Mount (BGA) |
EP2SGX90F1152C3N 1152-ball fineline bga (35 mm x 35 mm) Pin Configuration Guide
Pin configuration for EP2SGX90F1152C3N (1152-ball fineline bga (35 mm x 35 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2SGX90F1152C3N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2SGX90F1152C3N is suitable for 6 applications: 10 Gigabit Ethernet Line Cards, SONET/SDH Framer Backplanes, HD-SDI Video Routing Switchers, Radar and Electronic-Warfare DSP, Storage Area Network (SAN) Controllers, High-Speed Serial Protocol Bridging.
10 Gigabit Ethernet Line Cards
The EP2SGX90F1152C3N fits 10 Gigabit Ethernet line cards because its 12 multi-gigabit transceivers operate up to 6.375 Gbps, sufficient for multiple XAUI (4x3.125 Gbps) or single-lane 10GBASE-R aggregation channels when paired with an external PHY. The 90,960 logic elements and 192 18x18 multipliers handle MAC framing, statistics counters, and 10G classification logic; the 4.52 Mbit embedded RAM provides packet-buffer elasticity. In practice, designers place the FPGA between the network processor and SFP+ cages, leveraging the BGA's 558 user I/Os for parallel side-band interfaces, MDIO, and PTP timestamping.
Recommended
SONET/SDH Framer Backplanes
The EP2SGX90F1152C3N suits SONET/SDH OC-192 framer designs because its 6.375 Gbps transceivers map directly onto STS-192 / STM-64 serial links, while the 90nm ALM fabric implements framer overhead insertion, pointer adjustments, and section/line protection switching. The 4,548 LABs provide ample capacity for virtual-container concatenation and performance monitoring. Engineers typically instantiate the FPGA alongside a clock-and-data recovery PLL, using the BGA's differential I/O banks for jitter-clean serial interconnect. The C3 speed grade is adequate because SONET framer logic is largely parallel and clocked below 200 MHz.
Recommended
HD-SDI Video Routing Switchers
The EP2SGX90F1152C3N fits broadcast HD-SDI video routers because its multi-gigabit transceivers serialize and de-serialize SMPTE 292M (1.485 Gbps) and SMPTE 424M (2.97 Gbps) streams natively, while the 558 user I/Os support large crosspoint switch fabrics in 64x64 or larger matrices. The embedded 18x18 multipliers handle de-interleaving and audio embedding/demuxing in real time. A typical design uses one FPGA per input card and one per output card, with the BGA's 35 mm footprint fitting standard openGear or similar broadcast chassis.
Recommended
Radar and Electronic-Warfare DSP
The EP2SGX90F1152C3N is well suited to radar and electronic-warfare digital signal processing because its 192 dedicated 18x18 multipliers and 4.52 Mbit of dual-port RAM directly accelerate FFT, pulse-compression, and digital-beamforming kernels. The 12 multi-gigabit transceivers stream digitized antenna data into the FPGA at rates up to 6.375 Gbps per lane, while the ALM fabric implements adaptive MTI filtering. Defense end-users typically deploy the device in VPX or VME form-factor boards with ruggedized heatsink assemblies mounted to the 1152-BGA's exposed die land.
Recommended
Storage Area Network (SAN) Controllers
The EP2SGX90F1152C3N fits Fibre Channel and SAS/SATA SAN controller cards because its 6.375 Gbps transceivers directly drive 4x Fibre Channel (4.25 Gbps) and 6G SAS links, while the ALM logic implements T10 DIF checksum engines and SCSI command translation. The 4.52 Mbit embedded RAM is sized for credit-based flow-control buffers across multiple initiator/target sessions. The BGA package exposes 558 user I/Os, enough to fan out to multiple SFP+ cages and a SAS expander backplane simultaneously.
Recommended
High-Speed Serial Protocol Bridging
The EP2SGX90F1152C3N serves as a multi-protocol bridge because its 12 transceivers can be split across different clock domains, simultaneously converting between protocols such as Aurora, Serial RapidIO, Interlaken, and proprietary chip-to-chip SerDes links. The 90,960 logic elements implement PCS adaptation, CRC insertion, and lane-striping logic without external devices. Designers commonly use this FPGA as a backplane gateway on ATCA or MicroTCA carrier cards, with the 1152-BGA's high pin count providing generous LVDS side-band signaling to companion ASICS.
Recommended
Recommended Products Summary
Engineering reference data for EP2SGX90F1152C3N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2SGX90EF1152C3N | EP2SGX90EF1152C4N | EP2SGX90EF1152C5N | EP2SGX90EF1152C4 | EP2SGX90EF1152C3 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 1152-BGA | 1152-BGA - same | 1152-BGA - same | 1152-BGA - same | 1152-BGA - same | 1152-BGA - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | C3 | C3 | C4 (~15% higher Fmax) | C5 (fastest) | C4 | C3 |
| Transceivers | Up to 12 | 12 | 12 | 12 | 12 | 12 |
| Transceiver Data Rate | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps | 6.375 Gbps |
| User I/O | 558 | 558 | 558 | 558 | 558 | 558 |
| Embedded RAM | 4.52 Mbit | 4.52 Mbit | 4.52 Mbit | 4.52 Mbit | 4.52 Mbit | 4.52 Mbit |
| Pb-Free (RoHS) | Yes ('N' suffix) | Yes | Yes | Yes | No | No |
Key Differentiators
- Largest package option in the EP2SGX90 family (vs EP2SGX90EF1508C5)
- Lowest-power speed grade for the EP2SGX90 die (vs EP2SGX90EF1152C5N)
- Drop-in compatibility with 'E' mask variants (vs EP2SGX90EF1152C3N)
Design Notes
The 1152-BGA package (35 mm x 35 mm, 1.0 mm pitch per Stratix II GX pin information file) demands an 8- to 12-layer PCB with stacked microvia or via-in-pad construction to fan out inner balls. Use 50-ohm controlled-impedance stripline for the multi-gigabit transceiver lanes with intra-pair skew under 1 ps and inter-pair length matching within 50 mils. Place AC-coupling capacitors (0.1 uF X7R) within 200 mils of the differential transmitter pair.
At full transceiver utilization (12 channels at 6.375 Gbps) and C3 speed grade, the EP2SGX90F1152C3N dissipates approximately 12 to 15 W. The 1152-BGA exposes a central die-attach pad that MUST be soldered to a copper thermal land of at least 25 mm x 25 mm with 4-6 thermal vias to inner ground planes. For industrial-temperature operation, attach a heatsink with thermal interface material rated for at least 0.2 C/W; airflow of 200 LFM is recommended.
Stratix II GX transceivers require a clean, low-jitter reference clock per the ALTGX Megafunction User Guide. Use a dedicated clock synthesizer (e.g., AD9523-1) with RMS jitter under 1 ps over the 12 kHz to 20 MHz band; route the reference on a clock-dedicated input pin with controlled-impedance isolation. Enable the on-die termination and pre-emphasis features per the Stratix II GX Transceiver Architecture chapter to compensate for FR4 channel loss.
Do NOT confuse the EP2SGX90F1152C3N (speed grade C3) with the higher-grade EP2SGX90F1152C5 (C5, fastest Fmax) when ordering - timing closure on critical paths fails silently if the wrong speed grade is loaded. Verify the suffix letter against the Quartus II compilation report. Also note that 1152-BGA devices are NOT footprint-compatible with the 1508-BGA packages used by higher-density Stratix II GX members; PCB migration between them requires a redesign.
Compliance Information
RoHS-compliant with 'N' suffix per Altera/Intel FPGA product markings. Industrial-temperature variants (I-grade) are available separately. AEC-Q100 not applicable for FPGAs in this category.
