EP910LC30T - 24-Macrocell Classic EPLD, 30ns, PLCC-44 | Intel
MPN: EP910LC30T ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910LC30T Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines the non-volatility of EPROM-based configuration with combinational and registered logic blocks. Within the broader IC hierarchy, an EPLD sits below modern FPGAs and CPLDs in density but above simple PAL/GAL devices, providing deterministic pin-to-pin timing useful for glue logic, address decoding, and state-machine replacement. The EP910 is one of the longest-lived members of the Classic family, originally introduced by Altera in the late 1980s and now supported in long-term supply by Rochester Electronics.
Key features include 24 macrocells, 450 equivalent gates, 33.3 MHz maximum operating frequency, 30 ns pin-to-pin propagation delay (commercial grade), 5 V CMOS supply, and erasable windowed UV-erase reprogrammability. The LC suffix indicates a low-power CMOS process variant, while the T suffix indicates Tape and Reel packaging. Pin counts include dedicated inputs, I/O pins, and global clock pins arranged around a central AND-OR programmable interconnect.
Technically, the EP910 architecture centers on a programmable AND array feeding a fixed OR array, with each macrocell containing a configurable flip-flop, feedback path, and output enable. This architecture yields predictable, deterministic timing that simplifies timing closure compared with newer SRAM-based FPGA fabrics. The device is in-system programmable via the Altera programming algorithm and supports the industry-standard JTAG-style boundary-scan test.
Typical applications include bus-interface glue logic, address decoding for legacy 80xx microprocessors, state-machine replacement, peripheral control logic, and industrial controller boards where 5 V-tolerant CMOS logic and deterministic timing are required. The 44-pin PLCC package suits both through-hole socket and surface-mount assembly.
When designing with the EP910LC30T, plan for a single 5 V rail, a programming header compatible with the Altera ByteBlaster or equivalent, and proper decoupling of VCC pins. Note that newer Altera/Intel MAX-series CPLDs are recommended for new designs; the EP910 family is intended for legacy support and long-lifecycle maintenance.
Drop-in alternatives for EP910LC30T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC30T (same form factor and footprint) — differing in Package, Propagation Delay (tPD), Supply Voltage (VCC), Device Family, Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LC-30
✅ Drop-In✓ In Stock
$22.5 / Unit
View Datasheet →EP910LC-30Y
✅ Drop-In✓ In Stock
$25.4 / Unit
View Datasheet →EP910LC-30T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.1 / Unit
View Datasheet →EP910LC-35
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →EP910LC-25
✅ Drop-In✓ In Stock
$2.2 / Unit
View Datasheet →EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910LC30T Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Logic Capacity | 450 equivalent gates |
| Macrocells | 24 |
| Propagation Delay | 30 ns (tpd) |
| Maximum Frequency | 33.3 MHz |
| Supply Voltage | 5 V |
| Process Technology | CMOS (LC low-power variant) |
| Programmable Elements | UV-erasable EPROM |
| Package | 44-pin PLCC (J-Lead), Tape and Reel |
| Mounting Type | Surface Mount |
| Programming Interface | Altera ByteBlaster-compatible |
| Manufacturer | Intel (formerly Altera); currently supplied by Rochester Electronics |
EP910LC30T Pin Configuration
| Pin 1 | I/O — Input/Output pin |
| Pin 2 | I/O — Input/Output pin |
| Pin 3 | I/O — Input/Output pin |
| Pin 4 | I/O — Input/Output pin |
| Pin 5 | I/O — Input/Output pin |
| Pin 6 | I/O — Input/Output pin |
| Pin 7 | I/O — Input/Output pin |
| Pin 8 | I/O — Input/Output pin |
| Pin 9 | I/O — Input/Output pin |
| Pin 10 | I/O — Input/Output pin |
| Pin 11 | I/O — Input/Output pin |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Input/Output pin |
| Pin 14 | I/O — Input/Output pin |
| Pin 15 | I/O — Input/Output pin |
| Pin 16 | I/O — Input/Output pin |
| Pin 17 | I/O — Input/Output pin |
| Pin 18 | I/O — Input/Output pin |
| Pin 19 | I/O — Input/Output pin |
| Pin 20 | I/O — Input/Output pin |
| Pin 21 | I/O — Input/Output pin |
| Pin 22 | I/O — Input/Output pin |
| Pin 23 | VCC — +5 V power supply |
| Pin 24 | I/O — Input/Output pin |
| Pin 25 | I/O — Input/Output pin |
| Pin 26 | I/O — Input/Output pin |
| Pin 27 | I/O — Input/Output pin |
| Pin 28 | I/O — Input/Output pin |
| Pin 29 | I/O — Input/Output pin |
| Pin 30 | I/O — Input/Output pin |
| Pin 31 | I/O — Input/Output pin |
| Pin 32 | I/O — Input/Output pin |
| Pin 33 | I/O — Input/Output pin |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — Input/Output pin |
| Pin 36 | I/O — Input/Output pin |
| Pin 37 | I/O — Input/Output pin |
| Pin 38 | I/O — Input/Output pin |
| Pin 39 | I/O — Input/Output pin |
| Pin 40 | I/O — Input/Output pin |
| Pin 41 | I/O — Input/Output pin |
| Pin 42 | I/O — Input/Output pin |
| Pin 43 | I/O — Input/Output pin |
| Pin 44 | VCC — +5 V power supply |
Typical Applications
EP910LC30T is suitable for 7 applications: Legacy 80xx Microprocessor Address Decoding, Industrial Controller Glue Logic, Peripheral Chip-Select and Bus Arbitration, State-Machine Replacement for Vintage Designs, 5 V System Memory and I/O Expansion, Long-Lifecycle Maintenance and Legacy Repair, Educational and Prototyping Platforms.
Legacy 80xx Microprocessor Address Decoding
The EP910LC30T's 24 macrocells and 30 ns pin-to-pin propagation delay make it well-suited for decoding the 16- or 20-bit address bus of legacy 80xx-family microprocessors. With 33.3 MHz maximum operating frequency and deterministic CMOS timing, the device delivers chip-select and memory-map decode logic without the timing variability of programmable interconnect fabrics. The 5 V single-supply operation matches the rail requirements of vintage CPU and peripheral ICs, eliminating level-shifters. Engineers commonly place the EP910LC30T between the CPU address bus and peripheral chip-enable pins to consolidate discrete 74xx-series decoder logic into a single reprogrammable device.
Recommended
Industrial Controller Glue Logic
In industrial PLC-style designs the EP910LC30T replaces banks of discrete SSI/MSI glue logic, including address latches, interrupt arbiters, and peripheral-control sequencers. The 450-gate capacity and 24-macrocell array comfortably host a small state machine plus combinational decode, while the 5 V tolerance interfaces directly to legacy CMOS peripherals without external translation. The UV-erasable EPROM configuration supports field reprogramming via standard Altera programming hardware, allowing firmware updates during long equipment lifecycles. Per the Altera Classic datasheet, the LC (low-power CMOS) variant draws minimal quiescent current, important for thermally-constrained control cabinets.
Recommended
Peripheral Chip-Select and Bus Arbitration
The EP910LC30T's deterministic 30 ns timing and 24 macrocells suit it for peripheral chip-select generation and bus-arbitration logic in multi-master systems. With dedicated I/O pins and registered macrocell outputs, the device can implement prioritized chip-enable strobes, DMA acknowledge sequencers, and wait-state generators in a single package. The 5 V CMOS interface matches the logic levels of legacy peripheral controllers and memory chips. According to the Altera Classic EPLD family datasheet, the registered macrocell feedback path simplifies state-machine implementation for bus-arbitration protocols.
Recommended
State-Machine Replacement for Vintage Designs
The EP910LC30T is widely used to consolidate state machines previously implemented with multiple 74xx-series flip-flops and PAL/GAL devices. Each macrocell provides a configurable D flip-flop with feedback, enabling efficient Mealy and Moore state-machine encoding. With 24 macrocells, complex multi-state sequences fit in a single device. The 33.3 MHz maximum frequency and 30 ns tpd support moderate-speed control loops typical of legacy instrumentation. Per the manufacturer datasheet, the deterministic pin-to-pin timing simplifies timing analysis compared with SRAM-based FPGA alternatives.
Recommended
5 V System Memory and I/O Expansion
The EP910LC30T provides memory-bank decoding and I/O-expansion logic for 5 V embedded systems where modern 3.3 V CPLDs cannot be used without level translation. Its 24 macrocells and 450-gate capacity handle bank-select logic for multiple SRAM/EPROM devices and parallel-port expansion. The 44-pin PLCC package offers ample I/O count (typically around 36 user I/O) for these glue-logic tasks. The LC variant's low quiescent current suits battery-backed industrial systems where standby power matters.
Recommended
Long-Lifecycle Maintenance and Legacy Repair
The EP910LC30T is the canonical long-lifecycle replacement part for legacy Altera Classic EPLD designs in industrial, aerospace, and military maintenance programs. Rochester Electronics continues to supply the part for multi-decade support contracts because the 5 V CMOS design and UV-erasable reprogrammability remain compatible with original system schematics. Per Rochester's long-term support program, the EP910LC30T is the recommended drop-in replacement for original Altera EP910LC-30T units that have exhausted their erase-cycle budget or suffered ESD damage.
Recommended
Educational and Prototyping Platforms
The EP910LC30T's simple programming algorithm and UV-erasable window make it a popular teaching example for digital-logic courses covering programmable logic fundamentals. Engineering students can implement state machines, decoders, and arithmetic units on the 24-macrocell array while learning the Altera Classic design flow. The 5 V supply and standard PLCC socket simplify breadboard and through-hole prototyping. Per the manufacturer datasheet, the EP910's deterministic timing helps students reason about propagation-delay budgets without the complexity of modern FPGA toolchains.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC30T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC-30 | EP910LC-30Y | EP910LC-35 | EP910LC-25 |
|---|---|---|---|---|---|
| Package | PLCC-44 (Tape & Reel) | PLCC-44 (Tray) - same footprint | PLCC-44 - same footprint | PLCC-44 - same footprint | PLCC-44 - same footprint |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Macrocells | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tpd) | 30 ns | 30 ns | 30 ns | 35 ns | 25 ns |
| Maximum Frequency | 33.3 MHz | 33.3 MHz | 33.3 MHz | 28.5 MHz | 40 MHz |
| Equivalent Gates | 450 | 450 | 450 | 450 | 450 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial | Commercial | Extended Industrial | Commercial | Commercial |
| Process Variant | LC (Low-power CMOS) | LC (Low-power CMOS) | LC (Low-power CMOS) | LC (Low-power CMOS) | LC (Low-power CMOS) |
Key Differentiators
- Tape-and-reel packaging format (vs EP910LC-30)
- Extended temperature grade option available (vs EP910LC-30Y)
- Balanced speed grade for typical glue logic (vs EP910LC-25 / EP910LC-35)
Design Notes
Estimated: The EP910LC30T operates from a single 5 V supply with VCC on PLCC pins 23 and 44 and GND on pins 12 and 34. Place a 0.1 uF decoupling capacitor as close as possible to each VCC pin, plus a bulk 10 uF tantalum or ceramic capacitor near the package to suppress switching transients. The LC variant draws lower quiescent current than the PC variant, which is important for battery-backed industrial systems. Per Altera Classic datasheet guidance, multiple VCC and GND pins must all be connected; floating a power pin can cause intermittent logic errors.
Use a standard 44-pin PLCC socket (through-hole or surface-mount) to allow field replacement and UV-erase window access for reprogramming. Keep programming and JTAG pins accessible if in-system programming is required. For high-speed designs, place a ground plane directly under the PLCC socket to reduce EMI. The EP910's deterministic pin-to-pin timing allows simple point-to-point routing without impedance-controlled traces.
Estimated: The EP910LC30T is a 5 V part - do not connect I/O pins directly to 3.3 V logic without a level translator. UV-erase window EPLDs have a finite erase-cycle budget (typically a few hundred cycles), so field updates must be planned carefully. Do not exceed 33.3 MHz on the global clock input or timing violations will occur. Confirm exact macrocell and pin assignments using the latest Altera Classic EPLD datasheet before committing to a PCB layout, since the original Altera datasheet predates modern documentation formats.
Route all VCC and GND pins with wide traces or copper pours to minimize voltage drop during high-toggle periods. Place bypass capacitors within 100 mils of the respective VCC pins. Keep I/O traces short and direct, especially for clock and registered outputs, to avoid transmission-line effects above 20 MHz. If using a 44-pin PLCC socket, ensure the socket footprint matches the standard 1.27 mm pitch PLCC-44 land pattern to avoid soldering defects during surface-mount assembly.
Compliance Information
Compliance information not present in verified web data. The EP910 family is a legacy product originally launched by Altera before modern RoHS/REACH compliance documentation was standardized; consult Rochester Electronics directly for current compliance documentation under their long-term support program.
