EP910LC44-30T - 24-Macrocell CMOS EPLD, 33ns, PQCC-44 | Altera
MPN: EP910LC44-30T β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910LC44-30T Overview
A CMOS Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic IC that combines the architectural simplicity of PAL-type logic arrays with erasable programming. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern CPLDs/FPGAs: EPLD -> PLD -> programmable logic -> logic IC -> semiconductor. They retain the programming on-chip even when powered down, which makes them useful for bootstrap configuration and legacy system replacement.
Key features include 12 dedicated inputs, 24 bidirectional I/O lines, and 2 external clock inputs that drive internal registers. The device supports a nominal 5V supply (4.75V to 5.25V) and offers 33ns pin-to-pin propagation delay (tPD) suitable for bus-interface and address-decoding tasks. It is built on advanced CMOS technology for low static power consumption and includes a programmable security bit to protect user logic from unauthorized readback. The PQCC-44 J-lead surface-mount package provides robust mechanical attachment and is rated for the commercial temperature grade.
The EP910LC44-30T uses a sum-of-products macrocell architecture: each macrocell contains a programmable AND array feeding an OR gate with a configurable flip-flop, allowing combinational or registered output. The 240 product terms feed the 24 macrocells via a global interconnect, and the device supports asynchronous clear, synchronous preset, and output enable control. Together with the erasable windowed package option in the family, this architecture enables iterative design and field reprogramming.
Typical applications include TTL/CMOS logic replacement, random-logic consolidation, address decoding for memory and peripheral buses, bus-multiplexing glue logic, and state-machine implementation in industrial control, telecom, and instrumentation equipment. The 33ns tPD also supports fairly high-speed control-plane paths in legacy 5V designs.
When designing with this device, observe the 5V supply tolerance (4.75V to 5.25V) and add a 0.1uF decoupling capacitor close to each VCC pin to suppress switching transients on the parallel macrocell outputs.
This page synthesizes distributor pricing, drop-in Altera/Intel Classic EPLD family alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP910LC44-30T β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LC44-30T (same form factor and footprint) β differing in Package, Supply Voltage (VCC), Propagation Delay (tPD), Programming Method, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP910LC44-30
β Drop-Inπ Reference alternative (not in catalog)
EP910LC44-25
β Drop-Inπ Reference alternative (not in catalog)
EP910LC44
β Drop-Inβ In Stock
$8.95 / Unit
View Datasheet βEP910LC30T
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEP910LC-30T
β Drop-Inβ In Stock
$7.1 / Unit
View Datasheet βEP910LC44-30T Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD |
| Logic Type | PAL-type CMOS EPLD (OT PLD) |
| Macrocells | 24 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 33 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) |
| Dedicated Inputs | 12 |
| I/O Lines | 24 (bidirectional) |
| Total Inputs | 36 |
| Total Outputs | 24 |
| External Clock Inputs | 2 |
| Programming Technology | CMOS, UV-erasable (windowed package in family) |
| Security Bit | Programmable (logic readback protection) |
| Operating Temperature Grade | Commercial |
| Package | PQCC-44 (Plastic Leaded Chip Carrier, J-bend) |
| Terminal Form | J-BEND |
| Package Code | QCCJ |
| Mounting Type | Surface Mount |
EP910LC44-30T Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 10 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 13 | GND β Ground |
| Pin 14 | INPUT β Dedicated input |
| Pin 15 | INPUT β Dedicated input |
| Pin 16 | INPUT β Dedicated input |
| Pin 17 | INPUT β Dedicated input |
| Pin 18 | INPUT β Dedicated input |
| Pin 19 | INPUT β Dedicated input |
| Pin 20 | INPUT β Dedicated input |
| Pin 21 | INPUT β Dedicated input |
| Pin 22 | INPUT β Dedicated input |
| Pin 23 | INPUT β Dedicated input |
| Pin 24 | INPUT β Dedicated input |
| Pin 25 | CLK2 β External clock input 2 |
| Pin 26 | CLK1 β External clock input 1 |
| Pin 27 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 28 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 29 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 30 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 31 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 32 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 33 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 34 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 35 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 36 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 37 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 38 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 39 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 40 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 41 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 42 | I/O β Bidirectional I/O pin (macrocell) |
| Pin 43 | VCC β +5V supply voltage |
| Pin 44 | I/O β Bidirectional I/O pin (macrocell) |
Typical Applications
EP910LC44-30T is suitable for 6 applications: Address Decoding for Memory and Peripheral Buses, TTL/CMOS Glue Logic Replacement, State Machine Implementation, Bus Multiplexing and Signal Routing, Legacy Industrial Control Replacement, Instrumentation Front-Panel Logic.
Address Decoding for Memory and Peripheral Buses
The EP910LC44-30T's 24 macrocells and 240 product terms make it well-suited for address-decoding logic between a microprocessor and memory/peripheral devices. Its 33ns tPD easily meets the setup-time requirements of legacy 8-bit and 16-bit buses such as 8086, 68k, and Z80, where chip-select signals must be generated within a single clock cycle. The 24 I/O lines can be allocated to a mix of address inputs (up to 24 lines) and chip-select outputs, eliminating multiple 74LS/74HC TTL decoder packages on the board. Designers typically instantiate one macrocell per chip-select, with the remaining macrocells handling wait-state generation or bus-acknowledge logic. The 5V supply and CMOS low-power design also keep the decoder section below 100 mW typical dissipation.
Recommended
TTL/CMOS Glue Logic Replacement
The EP910LC44-30T consolidates dozens of discrete 74LS, 74HC, and 74F TTL gates into a single 24-macrocell device, reducing board area and improving reliability in legacy 5V systems. Its 5V CMOS I/O is directly TTL-compatible, so input pins can be driven by 5V TTL outputs without level shifters. The PAL-type sum-of-products architecture maps cleanly to SOP logic equations, allowing direct translation of existing TTL schematics. With 240 product terms available, designers can implement wide AND-OR structures that would otherwise require cascaded TTL gates. The PQCC-44 package occupies roughly the same board area as 4-6 SOIC-14 TTL packages, providing 4x-6x logic-density improvement on the same PCB.
Recommended
State Machine Implementation
The EP910LC44-30T's macrocell flip-flops, combined with two dedicated clock inputs, support Moore and Mealy state machines with up to 24 states. Each macrocell's flip-flop provides asynchronous clear and synchronous preset, which are essential for safe power-on initialization in industrial controllers. The 33ns tPD plus flip-flop setup time fits comfortably inside one clock period for clock frequencies up to approximately 15 MHz in 5V systems. Designers commonly use this EPLD for vending-machine controllers, instrument front-panel sequencers, and printer paper-path controllers, where the program can be UV-erased and updated between design revisions without re-spinning the PCB.
Recommended
Bus Multiplexing and Signal Routing
The EP910LC44-30T handles 8-bit and 16-bit bus multiplexing, bus-switching, and signal-routing tasks by mapping data-path control logic into its macrocell array. Its 24 bidirectional I/O lines can be configured as inputs or outputs per pin, supporting bidirectional bus buffers and time-multiplexed address/data buses. With 5V CMOS I/O tolerance, the device can directly interface with 5V transceivers, memory devices, and microcontrollers. The 33ns propagation delay ensures that routed signals meet the hold-time requirements of downstream latches. Common uses include address/data demultiplexing for 8085-style buses, peripheral chip-select steering, and interrupt-priority encoders.
Recommended
Legacy Industrial Control Replacement
The EP910LC44-30T is widely used to replace obsolete 74-series and discrete-logic boards in legacy industrial controllers, programmable logic controllers, and process-control instruments. Its CMOS low-power design (typically under 100 mW) keeps thermal stress low inside sealed control cabinets, while the PQCC-44 J-lead package survives industrial shock and vibration better than older DIP-packaged PALs. With 5V supply tolerance matching original TTL power rails, the part can be retrofitted onto existing PCBs without power-supply redesign. The erasable programming window (on windowed package variants in the family) allows field updates when control algorithms change.
Recommended
Instrumentation Front-Panel Logic
The EP910LC44-30T implements front-panel scanning, key-debounce, and display-multiplexing logic in test-and-measurement instruments such as oscilloscopes, signal generators, and bench multimeters. Its 24 I/O lines support 7-segment or 14-segment display multiplexing, rotary-encoder decoding, and push-button keypads up to 4x4. The two dedicated clock inputs allow one clock for display multiplexing and a second for keypad scanning, eliminating external timer ICs. The 33ns tPD keeps display-flicker artifacts below human perception thresholds when refresh rates are set above 60 Hz.
Recommended
Recommended Products Summary
Engineering reference data for EP910LC44-30T β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LC44-30 | EP910LC44-25 | EP910LC44 | EP910LC30T | EP910LC-30T |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PQCC-44 (QCCJ, J-bend) | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same | PQCC-44 - same |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| I/O Lines | 24 | 24 | 24 | 24 | 24 | 24 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Pin-to-Pin Compatible | Yes (reference) | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in | Yes - drop-in |
Key Differentiators
- Highest-density 5V EPLD in PQCC-44 with 24 macrocells (vs EP610PC-25)
- Faster 25ns speed grade available in same package (vs EP910LC44-25)
- Two dedicated clock inputs for multi-clock designs (vs EP610 family EPLDs)
Design Notes
The EP910LC44-30T operates from a single 4.75V to 5.25V supply. Place a 0.1uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 43) and a bulk 10uF tantalum or aluminum capacitor near the supply trace. CMOS switching currents can produce significant VCC droop during simultaneous macrocell transitions, so keep the VCC trace short and wide (at least 0.5 mm). Adding a ferrite bead between the EPLD VCC pin and the upstream regulator improves noise margin on the 5V rail.
The PQCC-44 (J-bend, QCCJ) package requires careful PCB land-pattern design: pad width should be 0.6 mm with 1.0 mm pitch. Use NSMD (non-solder-mask-defined) pads for better solder-joint reliability under thermal cycling. Keep all signal traces at least 0.2 mm away from package edges to avoid solder bridging, and route high-speed clock signals (CLK1, CLK2) on the inner PCB layers with grounded reference planes to control impedance.
Do not drive EPLD input pins with voltages above 5.5V - the Classic EPLD family is not 5V-tolerant beyond absolute-maximum ratings, and over-voltage can permanently damage the CMOS input structures. Also, unused dedicated inputs must be tied to VCC or GND (never left floating) to prevent oscillation and extra ICC current. The erasable windowed package variants must be shielded from ambient UV light in field installations to prevent inadvertent erasure.
Compliance Information
Compliance status not specified in verified data; classic EPLD family was originally designed for 5V commercial systems. Lifecycle status: obsolete. RoHS/REACH versions not separately listed in the verified data; refer to manufacturer datasheet for specific compliance markings on current factory stock.
