EP910LI-40T - 24 Macrocells Classic EPLD, 40ns | Altera / Intel
MPN: EP910LI-40T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
EP910LI-40T Overview
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that uses EPROM or EEPROM cells to store configuration, allowing the device to be erased with ultraviolet light and reprogrammed many times. EPLDs sit in the programmable logic hierarchy below modern CPLDs (Complex PLDs) and FPGAs, but they offer deterministic timing, low quiescent power, and simple development flows well suited to glue logic, state-machine replacement, and bus-interface decoding in legacy industrial systems. The EP910 family represents Altera's mid-density Classic tier above the EP610 and below the EP1800, providing balanced logic density for medium-complexity designs.
Key features of the EP910LI-40T include 24 macrocells, 24 I/O pins, 12 dedicated inputs, 240 product terms, 40 ns tPD propagation delay, CMOS low-power technology, UV-erasable windowed ceramic or plastic package options, and JTAG-free programming via the Altera programming algorithm. The device operates from a single 5 V supply typical of TTL-era logic and is housed in a 40-pin ceramic DIP (J44) or PLCC (J68) package depending on suffix. Industrial temperature range (-40C to +85C) makes it suitable for factory automation and outdoor equipment.
Typical applications include bus-interface decoding (address decoding for 8086, 68k, MIPS systems), state-machine replacement, custom peripheral controllers, vintage computer motherboard glue logic, and industrial control legacy equipment. Its deterministic 40 ns delay and 5 V CMOS compatibility make it ideal for replacing discrete 74LS/74HC logic arrays with a single integrated solution, simplifying PCB layout and reducing board area.
When designing with the EP910LI-40T, engineers must use Altera's legacy MAX+PLUS II or AHDL development environment (modern Intel Quartus does not support Classic EPLDs), which requires Windows XP or DOS-era emulation. Programming requires a Master Programming Unit (MPU) or compatible third-party programmer, as the device predates JTAG and modern ISP interfaces. Designers should verify availability through authorized distributors as the Classic EPLD family has been NRND for over a decade.
Drop-in alternatives for EP910LI-40T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910LI-40T (same form factor and footprint) — differing in Package, Operating Temperature, Technology, Family, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910LI-40
✅ Drop-In✓ In Stock
$12.9 / Unit
View Datasheet →EP910LI-35T
✅ Drop-In✓ In Stock
$28.5 / Unit
View Datasheet →EP910LI-35
✅ Drop-In✓ In Stock
$25.8 / Unit
View Datasheet →EP910LC-40T
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP910LC-40
✅ Drop-In✓ In Stock
$52 / Unit
View Datasheet →EP910LI-40T Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Maximum Inputs | 36 |
| Maximum Outputs | 24 |
| Product Terms | 240 |
| Propagation Delay (tPD) | 40 ns |
| Technology | CMOS, UV-erasable EPROM |
| Supply Voltage | 5 V (typical) |
| Operating Temperature | -40C to +85C (Industrial) |
| Architecture | PAL-type with global bus |
| Package | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG |
EP910LI-40T Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 0) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 18 | I/O — Bidirectional I/O pin (macrocell 16) |
| Pin 19 | I/O — Bidirectional I/O pin (macrocell 17) |
| Pin 20 | I/O — Bidirectional I/O pin (macrocell 18) |
| Pin 21 | INPUT — Dedicated input pin 0 |
| Pin 22 | INPUT — Dedicated input pin 1 |
| Pin 23 | INPUT — Dedicated input pin 2 |
| Pin 24 | INPUT — Dedicated input pin 3 |
| Pin 25 | INPUT — Dedicated input pin 4 |
| Pin 26 | INPUT — Dedicated input pin 5 |
| Pin 27 | INPUT — Dedicated input pin 6 |
| Pin 28 | INPUT — Dedicated input pin 7 |
| Pin 29 | INPUT — Dedicated input pin 8 |
| Pin 30 | INPUT — Dedicated input pin 9 |
| Pin 31 | INPUT — Dedicated input pin 10 |
| Pin 32 | INPUT — Dedicated input pin 11 |
| Pin 33 | I/O — Bidirectional I/O pin (macrocell 19) |
| Pin 34 | I/O — Bidirectional I/O pin (macrocell 20) |
| Pin 35 | I/O — Bidirectional I/O pin (macrocell 21) |
| Pin 36 | I/O — Bidirectional I/O pin (macrocell 22) |
| Pin 37 | I/O — Bidirectional I/O pin (macrocell 23) |
| Pin 38 | VCC — 5 V power supply |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Typical Applications
EP910LI-40T is suitable for 6 applications: Vintage Computer Motherboard Glue Logic, Industrial Control Legacy Replacement, Custom Peripheral Controllers, Bus Address Decoding for 16-bit Microprocessor Systems, State-Machine Replacement in Telecom Equipment, Retro-Computing and Hobbyist Projects.
Vintage Computer Motherboard Glue Logic
The EP910LI-40T's 24 macrocells and 40 ns propagation delay make it ideal for replacing discrete 74LS/74HC glue-logic arrays in vintage computer motherboards based on Intel 8086/8088, Motorola 68000, or early MIPS R2000/R3000 processors. With 24 bidirectional I/O pins and 12 dedicated inputs, a single EP910LI-40T can replace 5-10 discrete TTL packages implementing address decoding, wait-state generation, and bus-control signal conditioning. The 5 V CMOS supply matches the TTL logic rails typical of late-1980s/early-1990s motherboards, and the 40 ns delay fits within a 10 MHz system clock period with comfortable margin. Designers maintaining legacy hardware or producing retro-computing replicas benefit from a single integrated solution that simplifies PCB layout and reduces board area compared to discrete logic. The industrial temperature range also supports industrial-control single-board computers based on the same processor architectures.
Recommended
Industrial Control Legacy Replacement
The EP910LI-40T's industrial temperature range (-40C to +85C) and 40 ns deterministic timing make it suitable for industrial control equipment where replacement of failed Classic EPLDs is required to keep production lines running. Examples include CNC machine controllers, programmable logic controllers (PLCs), and process-control instrumentation designed in the 1990s that still uses Altera Classic EPLDs as state machines and bus arbiters. The 24 macrocells provide enough logic capacity for medium-complexity sequencing functions, while the 240 product terms support multi-input combinatorial logic typical of state-machine and decoder functions. The 5 V CMOS supply integrates with the existing industrial bus infrastructure without level shifters, and the L (low-power) CMOS technology minimizes heat dissipation in sealed enclosures. Replacement stock is critical because equipment lifecycles of 20+ years are common in factory automation, and the EP910 family has been NRND for over a decade.
Recommended
Custom Peripheral Controllers
The EP910LI-40T is well-suited to implementing custom peripheral controllers for legacy I/O expansion cards, ISA bus cards, and VMEbus modules used in industrial and embedded computing. With 24 macrocells, the EP910LI-40T can implement a complete ISA-bus peripheral interface including address decoding, interrupt acknowledge, DMA handshake, and read/write control logic in a single chip. The 40 ns propagation delay fits comfortably within an 8 MHz ISA bus cycle (125 ns), leaving more than 60 ns of timing margin for the rest of the interface logic. The 24 I/O pins support up to 16-bit data bus plus 8 control signals, while the 12 dedicated inputs accommodate address lines and bus-arbitration signals. Designers can implement custom functions such as parallel I/O expansion, serial-port emulators, or proprietary data-acquisition interfaces using AHDL or schematic entry with the legacy MAX+PLUS II toolchain.
Recommended
Bus Address Decoding for 16-bit Microprocessor Systems
The EP910LI-40T's 24 macrocells and 240 product terms make it well-suited for implementing address decoders for 16-bit microprocessor systems such as Intel 80286, Motorola 68020, or Zilog Z8000-based designs. A single EP910LI-40T can decode multiple chip-select signals for memory and peripheral banks, replacing 4-8 discrete 74LS138/139 decoder packages and saving significant board area. The 12 dedicated inputs can accommodate up to 24 address lines via internal expansion (using macrocell feedback to the array), while the 24 I/O pins drive chip-select outputs with sufficient drive strength for TTL loads. The 40 ns propagation delay fits within typical 16-bit bus cycle times of 125-250 ns depending on clock rate. With deterministic CMOS timing, designers can guarantee no metastability issues in the decoder path, unlike asynchronous discrete-logic implementations.
Recommended
State-Machine Replacement in Telecom Equipment
The EP910LI-40T serves well as a state-machine replacement in telecom equipment from the early 1990s, including PBX line cards, ISDN terminal adapters, and early cellular base-station controllers. The 24 macrocells can implement complex multi-state sequencers with 8-16 states and 4-8 outputs, with the remaining macrocells handling input conditioning and output decoding. The deterministic 40 ns tPD is well-matched to the timing requirements of telecom control planes operating at 8 kHz-2 MHz control rates, where predictability matters more than raw speed. The 5 V CMOS supply and industrial temperature range suit central-office and outdoor-cabinet environments. Many telecom OEMs built equipment with 20+ year lifecycles, and EP910LI-40T replacement stock is essential for keeping this infrastructure operational. The UV-erasable EPROM technology also allows in-system reprogramming via field-service programming equipment.
Recommended
Retro-Computing and Hobbyist Projects
The EP910LI-40T is popular in retro-computing and hobbyist projects for replicating or extending vintage computer architectures such as the original IBM PC, Apple II expansion cards, Commodore 64 cartridges, and Sinclair ZX Spectrum peripherals. The Classic EPLD can implement custom video controllers, memory expansions, or coprocessor interfaces that integrate with the host system's 5 V TTL bus. The 24 macrocells are enough to implement a custom character generator, sprite engine, or sound-chip emulator in a single device, while the 40 ns tPD matches the 1-4 MHz clock rates typical of 8-bit retro computers. Hobbyists value the device's ability to be erased with UV light and reprogrammed many times, enabling iterative design. The Altera MAX+PLUS II toolchain (still freely available as legacy software) supports schematic capture and AHDL entry, which is accessible to hobbyists without HDL expertise.
Recommended
Recommended Products Summary
Engineering reference data for EP910LI-40T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910LI-40 | EP910LI-35T | EP910LI-35 | EP910LC-40T | EP910LC-40 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 40-pin DIP / 44-pin PLCC, Tape & Reel | 40-pin DIP / 44-pin PLCC, Tube | 40-pin DIP / 44-pin PLCC, Tape & Reel | 40-pin DIP / 44-pin PLCC, Tube | Ceramic windowed, Tape & Reel | Ceramic windowed, Tube |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 40 ns | 40 ns | 35 ns | 35 ns | 40 ns | 40 ns |
| I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Approx. Unit Price (qty 1000) | $9.75 | $9.50 | $11.20 | $10.80 | $14.50 | $14.00 |
Key Differentiators
- Tape-and-reel packaging for high-volume SMT assembly (vs EP910LI-40)
- Industrial temperature range for harsh environments (vs EP910LC-40T)
- Lower-cost option in EP910 family (vs EP910LI-35T)
Design Notes
The EP910LI-40T is part of the legacy Altera Classic EPLD family and is NRND (Not Recommended for New Designs). Engineers must use the MAX+PLUS II development environment (version 10.x or earlier), which is only compatible with Windows XP or DOS-emulation environments. Modern Intel Quartus software does NOT support Classic EPLDs. Programming requires an Altera Master Programming Unit (MPU) or a compatible third-party programmer such as the BP-1200, as the device has no JTAG interface. New designs should use modern MAX II, MAX V, MAX 10, or Lattice ispMACH 4000 CPLDs instead.
For the EP910LI-40T in 40-pin DIP package, place a 0.1 uF decoupling capacitor as close as possible to the VCC pin (pin 38) with the ground lead connected to a low-impedance ground plane. Add a 10 uF bulk tantalum or electrolytic capacitor on the VCC rail near the device. All unused dedicated inputs should be tied to ground through 10 kohm resistors (not left floating) to prevent noise coupling. Output enable and clock inputs should be routed away from high-frequency switching signals to minimize crosstalk. The DIP package has a typical thermal resistance of approximately 50 C/W, so no heatsinking is required at the device's modest power dissipation (typically <500 mW at 5 V).
The EP910LI-40T operates from a single 5 V supply (typical VCC range 4.75 V to 5.25 V). The "L" designation indicates low-power CMOS technology with quiescent current typically under 50 mA. Add active power (Icc) increases proportionally to the toggle rate of the I/O and logic; estimate Icc_total = Icc_quiescent + 0.5 mA per MHz of switching frequency per I/O pin. For a design with all 24 I/O toggling at 10 MHz, total Icc may reach 120-150 mA. Design the 5 V regulator with at least 200 mA headroom. The device does not have a power-down or sleep mode, so any unused EP910 in a multi-EPLD design will still draw quiescent current.
Compliance Information
RoHS, REACH, lead-free, and halogen-free compliance status for the EP910LI-40T is [DATA_NEEDED]. The Altera Classic EPLD family was originally released before modern environmental compliance directives were established; many Classic parts were offered in leaded ceramic packages. Contact Intel/Altera legacy product support for current compliance documentation.
