EP610PC-20T - 16-Macrocell Classic EPLD, 20ns, PDIP-24 | Intel
MPN: EP610PC-20T ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.8 | $980.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.2 | $7,200.00 |
EP610PC-20T Overview
A CPLD/EPLD is a non-volatile programmable logic device that retains its configuration when power is removed, sitting in the broader hierarchy of programmable logic devices (PLD) -> CPLD -> EPLD -> programmable logic IC. Classic EPLDs predate modern flash-based CPLDs and are widely used for board-level integration of random logic, address decoding, bus arbitration, and peripheral control in industrial, telecom, and military systems where 5 V tolerance and proven long-term reliability are required.
Key features of the EP610PC-20T include 16 macrocells, 16 dedicated inputs plus pin feedback, 4 product-term OR arrays, a 5 V VCC supply, a 20 ns tPD commercial-grade speed grade, and on-board logic test circuitry that allows verification of function and AC specifications during standard production flow. The 'PC' suffix denotes the PDIP package, '20' denotes the 20 ns speed grade, and the 'T' indicates tape-and-reel packaging. The device is programmed using the MAX+PLUS II development system and supports the Classic-series JTAG-compatible programming interface.
The EP610PC-20T is built on a CMOS EEPROM/EPROM-based architecture with on-chip charge pumps for in-system programming, programmable interconnect, and product-term logic arrays per macrocell. Each macrocell contains a programmable register, feedback path, and output enable control. Designers can synthesize combinational or registered logic up to 300 gates equivalent, replacing dozens of discrete 74-series TTL/CMOS parts.
Typical applications include 5 V address decoding, glue logic for ISA/VME bus systems, state-machine replacement in industrial controllers, microcontroller I/O and peripheral expansion, and legacy telecom line-card interface logic. The through-hole PDIP-24 package is well suited to through-hole PCB assembly, prototype boards, and MIL-spec or ruggedized designs.
When designing with the EP610PC-20T, remember that Classic EPLDs use the legacy MAX+PLUS II toolchain; modern Quartus support is limited. Decoupling 0.1 uF ceramic caps must be placed on every VCC/GND pair, unused inputs must be tied to VCC through a 10 kohm resistor, and the device must be erased under UV light before reprogramming.
This page synthesizes distributor pricing, drop-in same-brand speed-grade alternatives, pinout diagrams, and practical design notes that are not aggregated on the manufacturer datasheet or single distributor listings, giving engineers a single decision-grade reference.
Drop-in alternatives for EP610PC-20T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610PC-20T (same form factor and footprint) — differing in Package, Supply Voltage (VCC), Operating Temperature, Propagation Delay (tPD), RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610PC-20
✅ Drop-In✓ In Stock
$47.8 / Unit
View Datasheet →EP610PC-15
✅ Drop-In✓ In Stock
$17.5 / Unit
View Datasheet →EP610IPC-25
✅ Drop-In✓ In Stock
$8.85 / Unit
View Datasheet →EP610IPC-10
✅ Drop-In✓ In Stock
$16.4 / Unit
View Datasheet →EP610ILI-12
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EP610PC-20T Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells |
| Usable Gates | 300 gates |
| Propagation Delay (tPD) | 20 ns |
| Maximum Frequency (fMAX) | 62.5 MHz |
| Pipelined Data Rate | up to 100 MHz |
| Supply Voltage (VCC) | 5 V |
| Number of Dedicated Inputs | 16 |
| Number of I/O Pins | 16 |
| Programmable Output Enable | Yes (per macrocell) |
| Package | 24-pin PDIP (Plastic DIP) |
| Mounting Type | Through-Hole |
| Operating Temperature | 0C to +70C (Commercial) |
| Programming Technology | UV-erasable EPROM, CMOS |
| Development Tool | MAX+PLUS II |
| RoHS Status | unknown |
EP610PC-20T Pin Configuration
| Pin 1 | INPUT/GCLK1 — Dedicated input or global clock 1 |
| Pin 2 | INPUT/OE2 — Dedicated input or output enable 2 |
| Pin 3 | INPUT — Dedicated input pin |
| Pin 4 | INPUT — Dedicated input pin |
| Pin 5 | INPUT — Dedicated input pin |
| Pin 6 | INPUT — Dedicated input pin |
| Pin 7 | INPUT — Dedicated input pin |
| Pin 8 | INPUT — Dedicated input pin |
| Pin 9 | INPUT — Dedicated input pin |
| Pin 10 | INPUT — Dedicated input pin |
| Pin 11 | INPUT — Dedicated input pin |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Macrocell I/O pin |
| Pin 14 | I/O — Macrocell I/O pin |
| Pin 15 | I/O — Macrocell I/O pin |
| Pin 16 | I/O — Macrocell I/O pin |
| Pin 17 | I/O — Macrocell I/O pin |
| Pin 18 | I/O — Macrocell I/O pin |
| Pin 19 | I/O — Macrocell I/O pin |
| Pin 20 | I/O — Macrocell I/O pin |
| Pin 21 | I/O — Macrocell I/O pin |
| Pin 22 | I/O — Macrocell I/O pin |
| Pin 23 | I/O — Macrocell I/O pin |
| Pin 24 | VCC — +5V supply voltage |
Typical Applications
EP610PC-20T is suitable for 6 applications: 5V Address Decoding Logic, Glue Logic Replacement for 74-series TTL, State Machine Controllers for Industrial Automation, Microcontroller Peripheral Expansion, Legacy Telecom Line-Card Interface Logic, Prototype and Educational Logic Design.
5V Address Decoding Logic
The EP610PC-20T is widely used as a 5V address decoder for legacy ISA, VME, and Multibus systems. Its 16 macrocells and 16 dedicated inputs can decode up to 16 address lines plus control signals like AEN, IOR, IOW into chip-select outputs for memory and peripheral banks. The 20 ns tPD is well within ISA bus timing budgets (typically 250 ns cycle), and the 5V VCC matches the bus voltage directly without level translation.
Recommended
Glue Logic Replacement for 74-series TTL
The EP610PC-20T can replace dozens of discrete 74LS, 74HC, and 74FTTL gates on a legacy board, integrating random logic into a single 24-pin PDIP. With 300 usable gates and 16 macrocells, designers consolidate address latches, bus buffers, interrupt arbiters, and parity generators into one programmable device. This reduces PCB area, lowers power consumption, and simplifies board rework compared to discrete TTL.
Recommended
State Machine Controllers for Industrial Automation
Each macrocell of the EP610PC-20T contains a programmable D flip-flop with feedback, enabling implementation of up to 16-state finite state machines for industrial sequencer logic. The 62.5 MHz fMAX supports high-speed sequencing of conveyor controllers, valve drivers, and motor-start logic. The through-hole PDIP-24 package withstands vibration better than SMD alternatives, making it suitable for factory-floor controllers and MIL-spec enclosures.
Recommended
Microcontroller Peripheral Expansion
The EP610PC-20T extends 8051, Z80, and 68HC11 microcontroller GPIO by implementing shift-register chains, PWM generators, keypad scanners, and LCD multiplexers in a single chip. The 16 macrocells can be partitioned into independent logic blocks driven by the host CPU, and the 5V VCC matches legacy MCU rails without translation. The 20 ns tPD supports polled peripheral interfaces with sub-microsecond response.
Recommended
Legacy Telecom Line-Card Interface Logic
The EP610PC-20T implements T1/E1 framer control, HDLC encoding, and line-card signaling in telecom infrastructure where 5V CMOS logic and proven long-term reliability are required. Its non-volatile UV-erasable configuration retains after power-down, eliminating boot ROM requirements for fixed-function line cards. The PDIP-24 package supports the through-hole assembly commonly used in telecom backplane designs.
Recommended
Prototype and Educational Logic Design
The EP610PC-20T remains popular in university digital-logic courses and breadboard prototyping because its through-hole PDIP-24 package fits standard IC sockets, and the MAX+PLUS II toolchain offers free student-license downloads. Students learn VHDL/Verilog-to-hardware synthesis targeting the EP610's 16 macrocells, gaining intuition for programmable logic fundamentals before transitioning to modern CPLD/FPGA toolchains.
Recommended
Recommended Products Summary
Engineering reference data for EP610PC-20T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610PC-20 | EP610PC-15 | EP610IPC-25 | EP610IPC-10 | EP610ILI-12 |
|---|---|---|---|---|---|---|
| Package | 24-pin PDIP | 24-pin PDIP | 24-pin PDIP | 24-pin PDIP | 24-pin PDIP | 24-pin PDIP |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 20 ns | 20 ns | 15 ns | 25 ns | 10 ns | 12 ns |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C | 0C to +70C | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Programming Technology | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | In-system programmable |
| Supply Voltage | 5V | 5V | 5V | 5V | 5V | 5V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Commercial temperature grade in PDIP-24 (vs EP610IPC-25)
- Faster speed grade vs the base EP610PC-20T (vs EP610PC-20)
- 20 ns tPD balances speed and cost (vs EP610PC-15)
Design Notes
The EP610PC-20T requires a single 5V VCC supply (4.75V to 5.25V). Place one 0.1 uF ceramic decoupling capacitor directly between VCC (pin 24) and GND (pin 12), with traces no longer than 5mm to the IC pins. Add a 10 uF tantalum bulk capacitor at the board supply entry point. The Classic EPLD draws approximately 50 mA ICC typical at 5V with all macrocells toggling; unused inputs tied to VCC through 10 kohm resistors prevent CMOS shoot-through current.
The 24-pin PDIP package has 2.54mm (0.100 inch) pin pitch and through-hole leads. Route all signal traces on inner layers with the PDIP-24 socket or direct PCB pads on the top layer; keep traces short to minimize reflections on the 16 dedicated input pins. Place the EP610PC-20T away from switching power supply inductors to avoid logic noise coupling. Maintain at least 2mm clearance from high-voltage or analog sections to preserve 5V digital noise margin.
Three pitfalls to avoid: (1) Do not interface 3.3V logic directly to EP610PC-20T I/O - the device is 5V-only and not 3.3V-tolerant; use a 74HCT125 or similar level translator. (2) Do not attempt to program the device using Quartus Prime - only MAX+PLUS II supports Classic EPLDs. (3) Do not skip UV erasure before reprogramming; accumulated charge on the EPROM cells requires a 30-minute UV-C exposure at 254 nm to fully reset. Failing to erase produces partial-programming errors that appear as intermittent logic faults.
Each of the 16 dedicated inputs has TTL-compatible thresholds (VIH = 2.0V, VIL = 0.8V) but the macrocell I/O pins are CMOS-compatible. To minimize ground bounce on the 24-pin PDIP, connect all GND (pin 12) and VCC (pin 24) pins directly to power planes, never via signal traces. If using a 20 MHz or faster external clock on GCLK1, route the clock trace first with 50 ohm characteristic impedance and keep it shorter than 50mm to prevent ringing.
Compliance Information
EP610PC-20T was launched in the early 1990s, predating RoHS requirements; the original datasheet does not specify RoHS compliance. For RoHS-compliant new designs, consider MAX II CPLDs. AEC-Q100 not applicable to legacy commercial EPLD; industrial-grade EP610IPC variants exist for non-automotive industrial use only.
