EPC1064LC20 - 65kb OTP Config PROM 20-PLCC | Intel
MPN: EPC1064LC20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
EPC1064LC20 Overview
A configuration PROM (also called a configuration device) is a non-volatile memory that holds the FPGA bitstream and reloads it at every power-up, reset, or reconfiguration event because SRAM-based LUT devices are volatile and lose their logic configuration when power is removed. Within the broader component hierarchy, configuration PROMs sit under Memory ICs > non-volatile memory > PROM, and are used in the boot path of every SRAM-based FPGA. The EPC1064LC20 occupies the OTP sub-category, trading re-programmability for low unit cost and a compact 20-PLCC footprint.
Key features of the EPC1064LC20 include 65,536 bits of storage (8,192 bytes), a serial data interface that streams configuration bits to the host FPGA on power-up, 5 V single-supply operation with 4.5 V to 5.5 V tolerance, and commercial-grade 0 C to 70 C temperature range. The 20-pin PLCC (LC) package provides a through-hole-compatible J-lead footprint that is widely supported on legacy development boards and easy to socket for factory programming or field replacement.
The EPC1064LC20 uses a simple internal state machine that streams configuration data out of an internal OTP array when the host FPGA asserts nSTATUS and drives DCLK, then tri-states after the DONE pin is released. Because the configuration clock is generated by the FPGA in passive-serial mode, no external oscillator is needed; the PROM simply shifts bits in lock-step with DCLK. The interface is intentionally minimal so the device can replace battery-backed configuration modules at a fraction of the BOM cost in low-to-mid density FPGA designs.
Typical applications for the EPC1064LC20 include boot memory for ACEX 1K and FLEX 10K designs, configuration storage for industrial controllers built around Stratix and APEX 20K, prototyping platforms using Mercury or APEX II FPGAs, and cost-sensitive legacy retrofits where the original EPC1064 has gone obsolete. Designers also use it as a single-chip boot source for multi-device FPGAs that accept passive serial configuration.
When designing with the EPC1064LC20, confirm that the host FPGA's configuration mode pins are strapped for passive-serial (PS) mode and that DCLK frequency stays within the PROM's ~10 MHz access budget. For new designs, prefer an EPCQ or EPCQ-L device in 16-pin SOIC for higher density and faster configuration; the EPC1064LC20 is best reserved for legacy PCB revs and exact-form-factor retrofits.
This page synthesizes distributor pricing, same-family OTP variants, and PCB-retrofit design notes for engineers maintaining or replicating EPC1064LC20-based systems.
Drop-in alternatives for EPC1064LC20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1064LC20 (same form factor and footprint) β differing in Memory Type, Package, Interface, Memory Size, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1441LC20
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPC1441LC20N
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPC1213LC20
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC1064PC8
β Drop-Inβ In Stock
$6.2 / Unit
View Datasheet βEPC1064LC20 Maximum Ratings & Electrical Characteristics
| Memory Size | 65 kb (65,536 bits) |
| Memory Type | OTP Configuration PROM (Flash-based, one-time programmable) |
| Programmable Type | OTP (One-Time Programmable) |
| Interface | Serial (Passive Serial / daisy-chain compatible) |
| Access Time | 90 ns (approximately 10 MHz) |
| Supply Voltage (Operating) | 4.5 V to 5.5 V |
| Supply Voltage (Nominal) | 5 V |
| Operating Temperature | 0 C to 70 C (Commercial) |
| Package / Case | 20-PLCC (LC) J-lead, 9x9 mm |
| No. of Terminals | 20 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Package Code | QCCJ (PLCC-20 J-lead) |
| Package Shape | Square |
| Compatible Altera FPGA Families | ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Modes Supported | Passive Serial (PS) with FPP up to 100 MHz on newer FPGAs |
| RoHS Status | Non-compliant (Sn/Pb finish) |
| Lead-Free | No (Sn/Pb terminal finish) |
EPC1064LC20 Pin Configuration
| Pin 1 | DATA β Serial data output to the host FPGA |
| Pin 2 | DCLK β Configuration clock input from the host FPGA |
| Pin 3 | nCONFIG β Configuration initiate (active low) |
| Pin 4 | nSTATUS β Status output to the host FPGA (active low) |
| Pin 5 | nCE β Chip enable input (active low) |
| Pin 6 | OE β Output enable input (active low) |
| Pin 7 | VCC β 5 V supply voltage |
| Pin 8 | GND β Ground |
| Pin 9 | NC β Not connected |
| Pin 10 | NC β Not connected |
| Pin 11 | NC β Not connected |
| Pin 12 | NC β Not connected |
| Pin 13 | NC β Not connected |
| Pin 14 | NC β Not connected |
| Pin 15 | NC β Not connected |
| Pin 16 | NC β Not connected |
| Pin 17 | NC β Not connected |
| Pin 18 | NC β Not connected |
| Pin 19 | NC β Not connected |
| Pin 20 | GND β Ground |
Typical Applications
EPC1064LC20 is suitable for 6 applications: ACEX 1K FPGA Boot Memory, FLEX 10K Configuration Storage, APEX 20K Industrial Controller Bitstream Source, Stratix / Stratix II Legacy Board Retrofit, FLEX 6000 Low-Density Logic Designs, Mercury Wireless Baseband Prototyping.
ACEX 1K FPGA Boot Memory
The EPC1064LC20 streams the ACEX 1K bitstream through the passive-serial interface at roughly 10 MHz, easily meeting the configuration bandwidth required by ACEX 1K devices with 65 kb of storage headroom. Its 5 V single-supply operation aligns with ACEX 1K VCCIO, removing the need for level shifters on the configuration bus. The 20-PLCC socket-friendly footprint simplifies factory programming using an Altera MasterBlaster or ByteBlaster cable. For most ACEX 1K designs the EPC1064LC20 delivers deterministic cold-boot behavior across 0 C to 70 C operation.
Recommended
FLEX 10K Configuration Storage
The EPC1064LC20 boots FLEX 10K FPGAs in passive-serial mode and supports daisy-chaining for larger FLEX 10K devices when 65 kb is not enough. With 4.5 V to 5.5 V supply tolerance and J-lead PLCC pins, the device tolerates the noisy 5 V rails common on industrial FLEX 10K boards. A 100 nF decoupling capacitor within 5 mm of VCC plus a 10 uF bulk capacitor on the 5 V rail suppresses supply ripple during configuration. The commercial 0 C to 70 C rating matches FLEX 10K industrial enclosure environments without pushing into extended-temperature territory.
Recommended
APEX 20K Industrial Controller Bitstream Source
Industrial controllers built around APEX 20K FPGAs use the EPC1064LC20 as a single-chip boot source for designs that fit within 65 kb of compressed bitstream. The passive-serial interface is driven by the FPGA, removing the need for an external oscillator and simplifying the BOM. APEX 20K designs that grow beyond 65 kb can daisy-chain a second EPC1064LC20 or migrate to an EPC1441LC20 on the same footprint. The Sn/Pb finish of the EPC1064LC20 suits industrial-grade boards that do not require RoHS compliance.
Recommended
Stratix / Stratix II Legacy Board Retrofit
The EPC1064LC20 supports Stratix and Stratix II FPGA configuration per the Altera configuration-device datasheet, but only through daisy-chain cascading because Stratix bitstreams exceed 65 kb. Engineers retrofitting legacy Stratix boards keep the EPC1064LC20 as a secondary boot device while populating additional EPC1064s or migrating to EPC1441LC20 in the same 20-PLCC socket. The 90 ns access time delivers roughly 11 Mbps sustained, sufficient for slow but reliable Stratix configuration when the FPGA drives DCLK below 10 MHz. Verify timing against the Stratix configuration user guide before deploying.
Recommended
FLEX 6000 Low-Density Logic Designs
FLEX 6000 designs typically compress below 65 kb, making the EPC1064LC20 an ideal single-chip boot source with no need for daisy-chaining. The 5 V supply and 0 C to 70 C range align perfectly with FLEX 6000 boards in consumer and industrial enclosures. Program the EPC1064LC20 once at the factory with the production bitstream and socket it onto the FLEX 6000 board for field-replaceable maintenance. The J-lead PLCC-20 package is easier to socket than QFN alternatives, simplifying depot-level board repair workflows.
Recommended
Mercury Wireless Baseband Prototyping
Mercury FPGA prototypes for wireless baseband signal processing use the EPC1064LC20 to hold the bitstream and reload it on every power-up, since SRAM-based LUT devices lose their configuration when the supply rail drops. The 90 ns access time translates to about 11 Mbps, which is more than adequate for single-device Mercury prototypes running under 100 MHz logic. The PLCC-20 socket allows engineers to swap PROM personalities during hardware bring-up, accelerating bitstream iteration. For production, migrate to EPC1441LC20 to gain headroom without changing the PCB layout.
Recommended
Recommended Products Summary
Engineering reference data for EPC1064LC20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1441LC20 | EPC1441LC20N | EPC1213LC20 | EPC1064PC8 |
|---|---|---|---|---|---|
| Brand | Intel (originally Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 20-PLCC (LC) 9x9 mm | 20-PLCC (LC) - same | 20-PLCC (LC) - same | 20-PLCC (LC) - same | 20-PLCC (LC) - same |
| Memory Size | 65 kb | 144 kb (+122%) | 144 kb (+122%) | 121 kb (+86%) | 65 kb (same) |
| Programmable Type | OTP | OTP | OTP | OTP | OTP |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Operating Temperature | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) | 0 C to 70 C (Commercial) |
| Access Time | 90 ns (~10 MHz) | 90 ns (~10 MHz) | 90 ns (~10 MHz) | 90 ns (~10 MHz) | 90 ns (~10 MHz) |
| Terminal Finish | Tin/Lead (Sn/Pb) | Tin/Lead (Sn/Pb) | Pb-free (NiPdAu) | Tin/Lead (Sn/Pb) | Tin/Lead (Sn/Pb) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| RoHS Status | Non-compliant (Sn/Pb) | Non-compliant (Sn/Pb) | Pb-free (compliant) | Non-compliant (Sn/Pb) | Non-compliant (Sn/Pb) |
Key Differentiators
- Lowest-cost 20-PLLC configuration PROM in the EPC1 family (vs EPC1441LC20)
- Pb-free option via the EPC1441LC20N sibling (vs EPC1441LC20N)
- Single-chip boot for low-density legacy FPGAs (vs EPC2LC20 (re-programmable configuration device))
Design Notes
Do not assume the EPC1064LC20 will support FPGAs larger than 65 kb of compressed bitstream. Stratix, Stratix II, and APEX II devices typically exceed this capacity and require daisy-chain cascading of multiple EPC1064s or migration to the higher-density EPC1441LC20 in the same 20-PLCC footprint. Always check the compressed bitstream size in the Altera Quartus programming file generator before committing to a single EPC1064LC20 design.
Decouple the EPC1064LC20 VCC pin with a 100 nF X7R ceramic capacitor placed within 5 mm of pin 7, and add a 10 uF bulk capacitor on the 5 V rail near the PROM. During configuration the PROM draws short bursts of current as it streams data, and inadequate decoupling can corrupt the bitstream mid-load. Estimated: peak configuration current is roughly 50 mA based on the Altera configuration-device datasheet typical characteristics; verify on the bench with a current probe.
Route the passive-serial lines DATA, DCLK, nCONFIG, nSTATUS, nCE, and OE as short direct traces (<= 50 mm) between the EPC1064LC20 and the host FPGA. Keep the configuration clock trace away from switching-power converter nodes and other high-di/dt signals to avoid coupling noise into the bitstream. The 90 ns access time of the PROM sets the upper bound on DCLK frequency, so route the clock trace with controlled impedance (50 ohm) if it exceeds 25 mm.
The EPC1064LC20 is rated for 0 C to 70 C commercial operation and draws modest supply current during configuration and standby. Estimated: in a 20-PLCC socket with natural convection, junction-to-ambient thermal resistance is around 60 C/W, so worst-case 50 mA at 5 V yields 250 mW dissipation and roughly 15 C rise above ambient - well inside the commercial limit. No heatsink is required, but ensure the PLCC socket contact area allows heat conduction into the PCB copper pour.
Compliance Information
Terminal finish is Sn/Pb per Verified Web Data; RoHS non-compliant. Reach, halogen-free, and conflict-minerals status not provided in the Verified Web Data and marked 'unknown'. AEC-Q100 not applicable (configuration PROM, not an automotive-grade IC).
