EPC1064VLC20 - 64Kb OTP FPGA Config PROM | Altera | 20-PLCC
MPN: EPC1064VLC20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.85 | $2.85 |
| 10 | $2.42 | $24.20 |
| 100 | $1.95 | $195.00 |
| 500 | $1.65 | $825.00 |
| 1,000 | $1.51 | $1,510.00 |
EPC1064VLC20 Overview
A configuration PROM is a non-volatile serial memory that holds the FPGA's configuration bitstream and streams it to the FPGA over a small handful of dedicated pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA) at power-up. In the broader component taxonomy, the EPC1064 sits under: configuration memory -> serial PROM -> non-volatile memory -> memory IC -> integrated circuit. It is a child of the EPC1 / EPC1064 family and a predecessor of the EPC1441, EPC2, EPC4, EPC8 and EPC16 successors that scaled density upward (EPC2 introduced 5 V in-system programmability to address the OTP limitation).
Key features include 64 Kbit storage organized as 64K x 1, a 5.0 V single-supply requirement, a serial daisy-chain output for cascading, and compatibility with essentially every legacy Altera SRAM-based LUT device family: ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX. Operating temperature range is 0C to 70C (commercial grade).
Architecturally the device uses an internal oscillator to clock data out of the one-time-programmable memory array; no external configuration clock source is required from the system. The daisy-chain protocol allows up to eight EPC1064 devices to be cascaded to support bitstreams up to roughly 512 Kbits without external steering logic. Programming is performed in a separate Altera programming unit before the part is soldered onto the board - the EPC1064 is not in-system programmable.
Typical applications include legacy Altera FPGA boot configuration on industrial controllers, telecom line cards using FLEX 10K or ACEX 1K, military/aerospace retrofits where original EPC1064-bitstreams are still in production, and replacement builds for EOL designs that must remain bit-identical. The 20-PLCC package is socket-friendly, simplifying field replacement in legacy systems.
When designing with this part, verify your target FPGA's configuration interface voltage (the EPC1064's 5 V VCC must match the FPGA's VCCIO for the configuration bank; older 5 V-tolerant FPGAs pair natively, while 3.3 V-only devices like Cyclone II require level shifting). Also confirm the cascaded PROM count does not exceed the FPGA's supported configuration clock frequency at startup. The OTP nature means any bitstream change requires a physical PROM swap - budget for that in field-service documentation.
This page consolidates distributor pricing as of 2026-09-10, drop-in compatible alternatives in the same 20-PLCC footprint, and practical design notes for integrating the EPC1064VLC20 into legacy Altera FPGA designs not found on a single manufacturer or distributor page.
Drop-in alternatives for EPC1064VLC20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC1064VLC20 (same form factor and footprint) β differing in Memory Type, Package, Memory Size, Interface, Operating Temperature.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC1064LC20
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPC1441LC20
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC1LC20
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPC1064VLC20 Maximum Ratings & Electrical Characteristics
| Memory Type | OTP (One-Time Programmable) Configuration PROM |
| Memory Size | 65,536 bit (64 Kb) |
| Organization | 64K x 1 (serial) |
| Interface | Serial, daisy-chain capable |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmable Type | OTP (factory programmed; not in-system programmable) |
| Package | 20-pin PLCC (J-lead, 9 x 9 mm) |
| Operating Temperature | 0C to +70C (commercial) |
| Compatible FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Cascade Support | Yes, daisy-chain output for up to 8 devices |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Programming Method | Altera programming hardware (factory, pre-solder) |
EPC1064VLC20 Pin Configuration
| Pin 1 | DATA_IN β Daisy-chain data input from upstream PROM |
| Pin 2 | DATA β Serial configuration data output to FPGA |
| Pin 3 | DCLK β Configuration clock input from FPGA |
| Pin 4 | nCONFIG β Configuration control from FPGA (active-low) |
| Pin 5 | nSTATUS β Status output to FPGA (active-low, open-drain) |
| Pin 6 | CONF_DONE β Configuration complete indicator (active-high) |
| Pin 7 | OE β Output enable for DATA driver |
| Pin 8 | MODE β Configuration mode select |
| Pin 9 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 10 | GND β Ground |
| Pin 11 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 12 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 13 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 14 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 15 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 16 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 17 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 18 | RESERVED β Tie to VCC or GND per datasheet |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | VCC β +5.0 V supply |
Typical Applications
EPC1064VLC20 is suitable for 6 applications: Legacy Altera FPGA Boot Configuration, Telecom Line Card Bitstream Storage, Industrial Controller Retrofit, Military and Aerospace Legacy Platforms, Test and Measurement Equipment, Bitstream-Equivalent Field Replacement.
Legacy Altera FPGA Boot Configuration
The EPC1064VLC20 stores the configuration bitstream for SRAM-based Altera FPGAs and streams it out at power-up over the nCONFIG / nSTATUS / CONF_DONE / DCLK / DATA interface. With 64 Kbit it matches legacy small-to-medium FPGA bitstreams (FLEX 10K, ACEX 1K, early Cyclone, FLEX 6000). The 5 V VCC matches the 5 V-tolerant configuration banks on these older devices, eliminating level shifters. Designers should still budget a 100 nF decoupling capacitor close to VCC and a 10 kohm pull-up on nSTATUS, and verify the FPGA's maximum DCLK frequency at configuration time - older Altera silicon caps DCLK well below 10 MHz, which the EPC1064's internal oscillator easily satisfies.
Recommended
Telecom Line Card Bitstream Storage
Telecom line cards built on FLEX 10K or APEX 20K FPGAs use the EPC1064VLC20 to store the boot bitstream and reconfigure the FPGA on hardware reset. The OTP nature is acceptable here because the bitstream is finalized during hardware bring-up and never changes in the field. The 20-PLCC socket-compatible package is critical in telecom because field-replacement of a corrupted PROM (e.g. after a board-level incident) must be possible without desoldering. Daisy-chain support lets designers stack two EPC1064VLC20s to support APEX 20K designs that exceed 64 Kbit, extending service life without re-architecting the board.
Recommended
Industrial Controller Retrofit
Industrial PLCs and motor controllers built on legacy Cyclone or ACEX 1K devices often contain EPC1064VLC20 PROMs that store the final certified bitstream and are not expected to change for the controller's 15-20 year service life. The OTP behavior is a feature here - it prevents accidental bitstream modification in the field. Engineers retrofitting these controllers must source authentic, traceable parts from authorized after-market distributors (Rochester Electronics LLC is the primary channel) to ensure bitstream equivalence and regulatory compliance. Verification includes reading back the programmed bitstream and comparing CRC against the golden image.
Recommended
Military and Aerospace Legacy Platforms
Military and aerospace platforms that were designed around Stratix, Stratix GX, or APEX II FPGAs in the early 2000s frequently still fly with EPC1064VLC20 configuration PROMs. The OTP property combined with a robust 20-PLCC package makes the part resistant to bit-flip events that could compromise mission-critical logic. The PLCC socket also allows depot-level replacement. New programs should migrate to modern in-system-programmable solutions such as EPC2 or EPCQ, but the EPC1064VLC20 remains a documented, supported source for sustaining engineering on fielded systems where re-validation costs dominate.
Recommended
Test and Measurement Equipment
Test and measurement instruments - logic analyzers, protocol exercisers, and bit-error-rate testers - frequently pair an EPC1064VLC20 with a FLEX 10K or ACEX 1K FPGA used for pattern generation or capture. The OTP PROM ensures the instrument's calibration and stimulus patterns are immutable across power cycles, which is required for regulatory-traceable measurements. Daisy-chain mode allows the same PROM pair to support both the data-acquisition FPGA and the front-panel display controller FPGA, simplifying BOM. Operating-temperature range of 0C to 70C is adequate for indoor laboratory and production-floor environments.
Recommended
Bitstream-Equivalent Field Replacement
When a fielded system fails because the configuration PROM has been damaged (ESD, thermal stress, package cracking), the EPC1064VLC20 must be replaced with a unit programmed with the identical bitstream. Authorized after-market distributors such as Rochester Electronics LLC stock factory-traceable parts and can supply them pre-programmed from the OEM's golden image. Engineers should always keep at least two spare programmed EPC1064VLC20 units per deployed system, because the OTP property means the part cannot be re-blanked and re-fused. Programming is performed on an Altera programming unit prior to board insertion.
Recommended
Recommended Products Summary
Engineering reference data for EPC1064VLC20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC1064LC20 | EPC1441LC20 | EPC2LC20 | EPC1LC20 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 20-PLCC (J-lead, 9x9 mm) | 20-PLCC (J-lead, 9x9 mm) - same | 20-PLCC (J-lead, 9x9 mm) - same | 20-PLCC (J-lead, 9x9 mm) - same | 20-PLCC (J-lead, 9x9 mm) - same |
| Density | 64 Kbit | 64 Kbit | 440 Kbit | 1.6 Mbit | 1 Mbit-class |
| Programmability | OTP (factory only) | OTP (factory only) | OTP (factory only) | In-system programmable (JTAG) | OTP (factory only) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Daisy-Chain Support | Yes (up to 8 devices) | Yes (up to 8 devices) | Yes | Yes | Yes |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete / NRND | Obsolete |
Key Differentiators
- Original Altera/Intel silicon, exact same die as EPC1064LC20 (vs EPC1064LC20)
- Smaller density than the EPC1441 and EPC2 family, with documented compatibility list (vs EPC2LC20)
- OTP behavior is a feature, not a limitation, for certified bitstreams (vs EPC2LC20)
Design Notes
The EPC1064VLC20 operates from a single 5.0 V supply (4.75 V to 5.25 V). Place a 100 nF decoupling capacitor as close as possible to the VCC pin (pin 20 on the 20-PLCC) with a short, wide ground return. The internal oscillator draws modest current during configuration, but the daisy-chain DATA driver can switch up to 8 EPC1064 devices in parallel during multi-PROM boot - budget for in-rush current on the 5 V rail and add a 10 uF bulk capacitor if the supply is shared with switching converters.
The 20-PLCC footprint accepts a standard PLCC IC socket, which is recommended for any deployment that may require field replacement (legacy telecom, industrial, mil/aero). When socketing, ensure the socket is a high-quality stamped or machined-pin type rated for the operating temperature and vibration profile. For soldered-down designs, follow standard J-lead reflow profile with peak temperature per J-STD-020 (typically 245C for SnAgCu); pre-bake the PLCC per MSL requirements if applicable.
Do not connect the EPC1064VLC20 directly to a 3.3 V-only FPGA configuration bank (e.g. Cyclone II without 5 V tolerance on CONF_DONE). The 5 V VCC and 5 V logic levels require either a 5 V-tolerant FPGA bank or a level translator on the configuration interface signals. Also remember the OTP property: any bitstream change requires a physical PROM swap with a unit pre-programmed on an Altera programming station - budget lead time and spares accordingly. [DATA_NEEDED: RoHS status] - if the target design requires RoHS, the EPC1064VLC20 may not be compliant and the EPC2LC20 or EPCS/EPCQ should be considered.
Route the DCLK trace from the FPGA to the EPC1064VLC20 as a short, impedance-controlled line (typically 50 ohm microstrip) with a series damping resistor near the FPGA if the trace exceeds 25 mm. Keep the DATA trace away from switching power nodes; the 5 V logic swing produces edges that can couple into adjacent analog or RF traces. Place the daisy-chain DATA_in from the upstream PROM adjacent to the DATA_out of the same package to minimize loop area, especially when cascading 4 or more EPC1064 devices.
Compliance Information
alterachips.com listing describes RoHS as 'non-compliant'; exact RoHS/REACH/lead-free status should be verified against the manufacturer datasheet before use in a regulated design. AEC-Q100 not applicable - this is a commercial-grade (0C to 70C) memory product, not an automotive-qualified IC.
