EPC2LC20EM - 1.6Mb Configurable PLD, 20-Pin PLCC | Intel
MPN: EPC2LC20EM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.95 | $129.50 |
| 100 | $10.85 | $1,085.00 |
| 500 | $9.2 | $4,600.00 |
| 1,000 | $7.95 | $7,950.00 |
EPC2LC20EM Overview
Programmable logic devices (PLDs) such as FPGAs normally require an external non-volatile boot-memory that holds the configuration bitstream at power-up. The EPC2 family replaced the older EPC1 generation with higher density, faster programming time, and an in-system programmability (ISP) interface that uses a 4-pin JTAG-compatible bus. By embedding configuration memory in a single 20-pin PLCC, designers eliminate the need for parallel EPROMs and reduce board area.
Key features of the EPC2LC20EM include 1.6 Mbit density, a parallel-mode or serial-mode data interface, dedicated nCS, nCLK, and DCLK pins, and an operating voltage of 3.3 V core. The PLCC-20 plastic package supports surface-mount reflow assembly and the industrial temperature range of -40C to +85C, making the part suitable for factory-floor, automotive, and outdoor telecom hardware that drives an Altera/Intel FPGA.
Typical applications include FPGA configuration-memory backup for prototyping and production boards, factory-floor industrial controllers based on Cyclone III/IV, communications line cards using Stratix or APEX 20K, and military or aerospace designs where data-retention and in-system reprogrammability over JTAG are required. The serial configuration interface reduces pin count to just DATA, DCLK, nCS, and nCONFIG, leaving FPGA I/O free.
When designing with the EPC2LC20EM, ensure that the JTAG chain length does not exceed the IEEE 1149.1 specification limits, allow at least 4 ms after power-up before configuration begins, and verify that the nINIT_CONF pin is correctly handled for multi-device cascading. Because the EPC2 family uses 3.3 V signaling, level translation may be required when driving 5 V-only FPGAs. This page synthesizes distributor stock, parameter reference data, and same-family alternatives not found in the manufacturer datasheet, helping engineers evaluate long-term sourcing.
Drop-in alternatives for EPC2LC20EM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20EM (same form factor and footprint) — differing in Mounting Type, Memory Type, Package, Interface, Programming Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LC120
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EPC2L20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$25.8 / Unit
View Datasheet →EPC2LC20EM Maximum Ratings & Electrical Characteristics
| Memory Type | Serial Configuration Memory (EPC2 family) |
| Density | 1.6 Mbit |
| Interface | Serial / Parallel configuration, JTAG ISP |
| Operating Voltage (Core) | 3.3 V |
| Programming Mode | In-system programmable via JTAG (IEEE 1149.1) |
| Package Type | PLCC-20 (plastic) |
| Operating Temperature | -40C to +85C (industrial) |
| Configuration Compatibility | Stratix, Cyclone, APEX, ACEX, FLEX, MAX, Excalibur, HardCopy |
| Mounting Type | Surface Mount (PLCC socket or solder) |
| Manufacturer Family | EPC2 Enhanced Configuration Device |
EPC2LC20EM Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA |
| Pin 2 | DCLK — Configuration clock input |
| Pin 3 | nCS — Chip select (active low) |
| Pin 4 | nCONFIG — Configuration control (active low) |
| Pin 5 | nSTATUS — Status output to FPGA |
| Pin 6 | nINIT_CONF — Initiate configuration (active low, chained) |
| Pin 7 | nCE — Chip enable for daisy-chain (active low) |
| Pin 8 | TDI — JTAG Test Data In |
| Pin 9 | TMS — JTAG Test Mode Select |
| Pin 10 | GND — Ground reference |
| Pin 11 | TCK — JTAG Test Clock |
| Pin 12 | TDO — JTAG Test Data Out |
| Pin 13 | OE — Output enable for parallel mode |
| Pin 14 | A0 — Address line / byte-mode select |
| Pin 15 | A1 — Address line / byte-mode select |
| Pin 16 | A2 — Address line / byte-mode select |
| Pin 17 | A3 — Address line / byte-mode select |
| Pin 18 | A4 — Address line / byte-mode select |
| Pin 19 | A5 — Address line / byte-mode select |
| Pin 20 | VCC — 3.3 V supply |
Typical Applications
EPC2LC20EM is suitable for 6 applications: Cyclone FPGA Configuration Memory, Stratix High-End FPGA Boot, Industrial Control Boards, Telecommunications Line Cards, Test and Measurement Instrumentation, Military and Aerospace FPGA Systems.
Cyclone FPGA Configuration Memory
The EPC2LC20EM stores the FPGA bitstream for Intel/Altera Cyclone III, Cyclone IV, and Cyclone V FPGAs that boot from a passive-serial configuration source. With 1.6 Mbit density it comfortably fits the largest Cyclone bitstreams (Cyclone IV EP4CE115 fits in ~3.9 Mbit, so multiple EPC2LC20EM devices are cascaded for big FPGAs). Placed adjacent to the FPGA on the PCB, the EPC2LC20EM serially clocks configuration data through DATA/DCLK lines at power-up, while the JTAG interface lets production engineers re-program the boot image without removing the device from the board - reducing field-rework cost.
Recommended
Stratix High-End FPGA Boot
High-end Stratix and APEX 20K FPGAs require external configuration memory for their multi-megabit bitstreams. The EPC2LC20EM, with its 1.6 Mbit density and 3.3 V core, is paired with these devices through the FPP (Fast Passive Parallel) interface to minimize boot time. Designers typically chain several EPC2 devices in series for bitstreams exceeding 1.6 Mbit, and the EPC2LC20EM's JTAG ISP chain enables in-system programming of the entire daisy-chain via a single 4-wire TAP.
Recommended
Industrial Control Boards
Factory-floor controllers and PLCs based on Intel FPGAs rely on the EPC2LC20EM's industrial -40C to +85C temperature range for reliable cold-start in unheated enclosures. The PLCC-20 socket allows easy field replacement if the boot image is ever corrupted, and the JTAG ISP interface supports on-board firmware updates without disassembling the controller. Power-rail sequencing, watchdog, and fail-safe boot logic are commonly implemented in the same FPGA and depend on the EPC2LC20EM delivering a known-good bitstream within 4 ms of nCONFIG assertion.
Recommended
Telecommunications Line Cards
Telecom line cards built around FLEX 10K and APEX 20KE FPGAs use the EPC2LC20EM as the central boot memory, allowing hot-swap of the configuration image when upgrading protocols (e.g., from TDM to packet-based fabrics). The 3.3 V core matches the FPGA's VCCIO rail, eliminating the need for level shifters, and the JTAG chain can be aggregated across all line-card FPGAs to enable card-level ISP from a single backplane TAP. Wide commercial availability at distributors such as DigiKey supports the long product lifecycles typical in telecom.
Recommended
Test and Measurement Instrumentation
Test equipment such as oscilloscopes, logic analyzers, and protocol testers use EPC2LC20EM-backed FPGAs to host reconfigurable measurement firmware. The in-system programmability lets the factory load a calibration image during burn-in, while service centers can update the bitstream via JTAG without opening the chassis. Designers value the PLCC-20's socket compatibility - a service technician can swap the boot memory in minutes if the original image becomes corrupted by a power-event glitch.
Recommended
Military and Aerospace FPGA Systems
Defense and aerospace programs that standardized on Altera FPGAs continue to use the EPC2LC20EM because of its long-term availability, industrial temperature grade, and JTAG ISP that supports MIL-STD-1553-style field updates. Programs that require lead-bearing solder typically order the -NAS suffix variant. Designers must plan for last-time-buy events: Intel has historically issued PCN-LTB notices for EPC2 devices, so long-lifecycle programs should stockpile or migrate to active-serial EPCQ memory before EOL.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20EM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20 | EPC2LC20N | EPC2LI20N | EPC2LC120 | EPC2L20 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Density | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit |
| Operating Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Configuration Compatibility | Stratix, Cyclone, APEX, ACEX, FLEX, MAX | Same FPGA families | Same FPGA families | Same FPGA families | Same FPGA families | Same FPGA families |
Key Differentiators
- Industrial temperature grade in the standard PLCC-20 footprint (vs EPC2LC20)
- Documented drop-in alternative with identical pinout (vs EPC2LI20N)
- In-system programmability eliminates parallel EPROM programmers (vs EPC1LC20)
Design Notes
The EPC2LC20EM requires a stable 3.3 V supply with at least 100 mA of headroom during in-system programming bursts. Place a 0.1 uF decoupling capacitor within 5 mm of the VCC pin and a 10 uF bulk capacitor on the same rail. The device will not drive the DATA pin correctly if VCC droops below 3.0 V during FPGA configuration; verify with an oscilloscope at the worst-case load step.
Route DATA, DCLK, and nCS as a matched-length bus (within 50 mils) and place the EPC2LC20EM within 25 mm of the target FPGA's configuration pins to minimize reflections. The PLCC-20 socket should be socketed (rather than soldered) on production boards to allow field replacement. Keep JTAG signals (TDI, TDO, TMS, TCK) away from switching power planes to avoid ISP programming errors.
Do not confuse the EPC2LC20EM (industrial grade, EM suffix) with the EPC2LC20 (commercial). Using the commercial variant in an outdoor enclosure will cause configuration failures at sub-zero temperatures. Also, ensure nINIT_CONF is correctly pulled high through a 10 kohm resistor - leaving it floating prevents multi-device daisy-chaining. Finally, remember that EPC2 is a legacy device: Intel has issued last-time-buy notices in the past, so secure long-term supply before committing to a new design.
Compliance Information
The Verified Web Data and Internal Database Data did not provide explicit RoHS, REACH, lead-free, halogen-free, or conflict-mineral statements for the EPC2LC20EM. Intel's product page generally lists EPC2 family devices as lead-free / RoHS-compliant for current production, but specific compliance documents were not returned by web search. Marked unknown to comply with data authenticity rules.
