EPC2LC20N-W - 1.6Mb In-System Prog Config PROM | Altera | PLCC-20
MPN: EPC2LC20N-W ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.5 | $11.50 |
| 10 | $10.2 | $102.00 |
| 100 | $8.95 | $895.00 |
| 500 | $7.6 | $3,800.00 |
| 1,000 | $6.45 | $6,450.00 |
EPC2LC20N-W Overview
A configuration PROM is a non-volatile memory that stores FPGA bitstream data and serially transfers it to the target FPGA at power-up via the DATA, DCLK, OE, and nCS handshake lines. In the broader hierarchy, the EPC2 sits under Altera's enhanced-configuration-device family (EPC4/EPC8/EPC16/EPC2/EPC1/EPC1441), which itself belongs to the FPGA-support ecosystem (configuration memory -> memory IC -> semiconductor). The 3.3V/5V dual supply, JTAG ISP support, and 1.6-Mbit density make the EPC2LC20N-W one of the most widely used legacy Altera configuration devices.
Key features include 1.6 Mbit EPROM density, serial configuration clock up to 66.7 MHz, in-system programmability through the JTAG (Joint Test Action Group) interface, 4-pin serial interface (DATA, DCLK, nCS, OE), and support for cascading with other EPC devices. The device is non-cascadable in the enhanced-configuration-device family when targeting newer high-density Stratix FPGAs; for those applications Altera recommends EPC4/EPC8/EPC16.
The EPC2LC20N-W uses an EPROM core that is erased by UV exposure (windowed package variants) and reloaded via JTAG. The internal address counter is clocked by DCLK from the target FPGA, while nCS and OE gate the tri-state DATA output. The combination of a small footprint and a robust serial protocol has made the EPC2 a de-facto standard for APEX 20K and ACEX 1K designs.
Typical applications include APEX 20K / ACEX 1K / FLEX 10K FPGA boot configuration, Stratix-series configuration on legacy boards, industrial control system FPGA boot memory, and test equipment FPGA bitstream storage. For designs migrating to Cyclone III/IV/V or Stratix V/10, Altera recommends newer configuration devices or active serial flash.
Designers should verify that the target FPGA is compatible with the EPC2 device family using the Altera Configuration Device Compatibility table before PCB layout. The 20-pin PLCC J-lead package requires a socket or reflow profile compatible with J-leaded devices.
This page synthesizes distributor pricing, drop-in alternatives, pinout data, and practical design notes not found in the manufacturer datasheet. Lifecycle, supply voltage, and pinout values are extracted verbatim from the Altera EPC2 Configuration Devices datasheet.
Drop-in alternatives for EPC2LC20N-W — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20N-W (same form factor and footprint) — differing in Package, Configuration Interface, Memory Type, Mounting Type, Function.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LI20N
✅ Drop-In✓ In Stock
$5.1 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2CC20N
✅ Drop-In✓ In Stock
$10.85 / Unit
View Datasheet →EPC22LC20N
✅ Drop-In📋 Reference alternative (not in catalog)
EPC2LC20N-W Maximum Ratings & Electrical Characteristics
| Memory Type | EPROM (UV-erasable, ISP) |
| Memory Size | 1.6 Mbit |
| Programmable Type | In System Programmable |
| Configuration Interface | Serial (DATA, DCLK, OE, nCS) |
| Internal Oscillator Frequency | 66.7 MHz |
| Supply Voltage (VCC) | 3.0 V to 3.6 V, 4.75 V to 5.25 V |
| ISP Interface | JTAG (IEEE 1149.1) |
| Supported FPGA Families | APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone |
| Package | 20-LCC (J-Lead) PLCC-20 |
| Mounting Type | Surface Mount |
| Packaging | Tape & Reel (-W suffix) |
| Cascade Support | Yes (with other EPC2 devices) |
| Pin Count | 20 |
EPC2LC20N-W Pin Configuration
| Pin 1 | DATA — Serial configuration data output to FPGA DATA0 |
| Pin 2 | DCLK — Configuration clock input from FPGA |
| Pin 3 | VCC — Power supply (3.3V or 5V) |
| Pin 4 | nCS — Chip select (active low) |
| Pin 5 | OE — Output enable (active high) |
| Pin 6 | NC — Not connected |
| Pin 7 | NC — Not connected |
| Pin 8 | NC — Not connected |
| Pin 9 | GND — Ground |
| Pin 10 | NC — Not connected |
| Pin 11 | NC — Not connected |
| Pin 12 | NC — Not connected |
| Pin 13 | TDI — JTAG test data input |
| Pin 14 | TMS — JTAG test mode select |
| Pin 15 | TCK — JTAG test clock |
| Pin 16 | TDO — JTAG test data output |
| Pin 17 | NC — Not connected |
| Pin 18 | NC — Not connected |
| Pin 19 | NC — Not connected |
| Pin 20 | VCC — Power supply (3.3V or 5V) |
Typical Applications
EPC2LC20N-W is suitable for 6 applications: APEX 20K FPGA Boot Configuration, ACEX 1K FPGA Configuration Memory, FLEX 10K FPGA Boot Memory, Stratix / Cyclone Series Configuration (Legacy Boards), Industrial Control System FPGA Boot, Test and Measurement Equipment Bitstream Storage.
APEX 20K FPGA Boot Configuration
The EPC2LC20N-W stores the 1.6-Mbit bitstream for APEX 20K-series FPGAs and delivers it serially at 66.7 MHz to the FPGA's DATA0/DCLK pins on power-up. The 20-pin PLCC J-lead package fits legacy APEX 20K development boards, and the dual 3.3V/5V supply (3.0V-3.6V or 4.75V-5.25V) allows direct interface with both 3.3V and 5V FPGA banks. Unlike parallel configuration PROMs, the serial handshake (DATA, DCLK, OE, nCS) requires only four signal pins, leaving more PLCC pins for JTAG and ground. For APEX 20K designs migrating to Cyclone III/IV/V, consider EPCQ or active-serial flash for better long-term availability.
Recommended
ACEX 1K FPGA Configuration Memory
The EPC2LC20N-W serves as the dedicated configuration PROM for ACEX 1K FPGAs in industrial-control and instrumentation designs. Its 1.6-Mbit EPROM density is sufficient for the largest ACEX 1K device (EP1K100), and the 3.0V-3.6V / 4.75V-5.25V dual supply allows operation with either ACEX 1K core voltage. The JTAG ISP interface lets engineers re-program the bitstream without removing the chip from the board, which is critical for ACEX 1K designs that undergo frequent firmware iteration. The 66.7 MHz internal oscillator ensures sub-second configuration times on power-up.
Recommended
FLEX 10K FPGA Boot Memory
The EPC2LC20N-W configures FLEX 10K FPGAs in legacy telecom, industrial-control, and test-instrumentation applications. With 1.6 Mbit of storage, the device supports the largest FLEX 10K members (EPF10K100A, EPF10K130E), and the 20-pin PLCC J-lead footprint matches FLEX 10K reference designs from Altera. The serial protocol (DATA, DCLK, OE, nCS) is identical to later configuration devices, simplifying migration to EPCQ or active-serial flash when FLEX 10K designs are updated. The dual 3.3V/5V supply makes the part drop-in compatible with both 5V and 3.3V FLEX 10K boards.
Recommended
Stratix / Cyclone Series Configuration (Legacy Boards)
The EPC2LC20N-W can configure early-generation Stratix (EP1S10/EP1S25) and Cyclone (EP1C3/EP1C6) FPGAs where the bitstream fits within 1.6 Mbit. For legacy boards already designed with the 20-pin PLCC footprint, the part provides a proven, drop-in configuration memory. The 66.7 MHz serial interface delivers configuration data fast enough for typical Cyclone bitstreams under 200 ms. For Stratix III/IV/V or Cyclone III/IV/V designs, EPCQ or active-serial flash should be considered for higher density and continued product availability.
Recommended
Industrial Control System FPGA Boot
The EPC2LC20N-W with the EPC2LI20N (industrial-grade) sibling suits factory-floor FPGA-based controllers requiring reliable boot memory. The 1.6-Mbit EPROM density supports mid-density control algorithms, and the JTAG ISP interface allows field updates of the FPGA bitstream without de-soldering the configuration PROM. The 20-pin PLCC J-lead package offers robust mechanical attachment suited to vibration-prone industrial environments. The dual 3.3V/5V supply (3.0V-3.6V or 4.75V-5.25V) integrates easily with 24V-bus-derived control rails.
Recommended
Test and Measurement Equipment Bitstream Storage
Test and measurement instruments based on APEX 20K or ACEX 1K FPGAs use the EPC2LC20N-W to store firmware bitstreams. Its 66.7 MHz configuration clock enables fast instrument boot, and the in-system programmability via JTAG allows firmware updates in factory calibration workflows. The 20-pin PLCC package is well suited to the through-hole/socket assembly often used in test equipment. The dual 3.3V/5V supply interface supports mixed-voltage signal chains found in mixed-signal test instruments.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20N-W — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LI20N | EPC2LC20 | EPC2CC20N | EPC22LC20N |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera | Altera | Altera | Altera | Altera |
| Package | 20-PLCC (J-Lead) | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same | 20-PLCC (J-Lead) - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit |
| Supply Voltage | 3.0V-3.6V / 4.75V-5.25V | 3.0V-3.6V / 4.75V-5.25V | 3.0V-3.6V / 4.75V-5.25V | 3.0V-3.6V / 4.75V-5.25V | 3.0V-3.6V / 4.75V-5.25V | 3.0V-3.6V / 4.75V-5.25V |
| Internal Oscillator | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz | 66.7 MHz |
| Temperature Grade | Commercial | Commercial | Industrial | Commercial | Commercial | Commercial |
| Packaging Format | Tape & Reel (-W) | Tube | Tube | Tube | Tube | Tube |
| ISP Interface | JTAG | JTAG | JTAG | JTAG | JTAG | JTAG |
Key Differentiators
- 1.6-Mbit density fits the largest APEX 20K and ACEX 1K devices (vs EPC1LC20N)
- Industrial temperature grade sibling available (vs EPC2LC20N-W (commercial))
- Dual 3.3V/5V supply eliminates level translation (vs 3.3V-only configuration PROMs)
Design Notes
The EPC2LC20N-W operates from a dual-rail supply (3.0V-3.6V or 4.75V-5.25V). Estimated: at 66.7 MHz internal-oscillator operation, peak VCC current during configuration can exceed 50 mA; place a 0.1 uF decoupling capacitor close to VCC pins (3 and 20) and a 10 uF bulk capacitor on the supply rail. Connect both VCC pins (3 and 20) to the same supply rail with a star topology to avoid ground-bounce issues during the configuration cycle.
The 20-pin PLCC J-lead package requires a socket or reflow profile compatible with J-leaded devices. Route DATA, DCLK, nCS, and OE as a tightly coupled bus to the FPGA; keep traces under 50 mm to avoid signal-integrity issues at 66.7 MHz. Use a dedicated ground plane beneath the PLCC footprint, and isolate the JTAG signals (TDI/TMS/TCK/TDO) from the configuration-data bus to prevent programming crosstalk.
Do not cascade the EPC2LC20N-W with EPC4/EPC8/EPC16 in enhanced-configuration-device mode; those parts are designed for non-cascaded single-device configuration of Stratix/Cyclone high-density FPGAs. The EPC2LC20N-W is intended for APEX 20K, ACEX 1K, and FLEX 10K families; verify FPGA compatibility in the Altera Configuration Device Compatibility table before PCB layout. Using an EPC2 for a Stratix V or Cyclone V target will result in configuration failure.
When the EPC2LC20N-W drives the FPGA DATA0 pin at 66.7 MHz, treat the DATA line as a 50-ohm controlled-impedance trace. Source-series termination of 33 ohms may be required if the trace length exceeds 25 mm to suppress ringing. Ensure the OE and nCS control signals are pulled high/low cleanly during power-up; floating OE can cause bus contention with the FPGA's configuration controller.
Compliance Information
RoHS/REACH compliance status for the -W suffix variant is not confirmed in available datasheets; verify with Altera/Intel product environmental compliance documentation before use in RoHS-restricted designs. EPC2 family is not AEC-Q100 qualified (logic/FPGA-support memory IC).
