EPC2LC20NUBAF48 - Altera 2Mb Config Device for SRAM FPGAs | FPGA
MPN: EPC2LC20NUBAF48 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $18.9 | $9,450.00 |
| 1,000 | $16.4 | $16,400.00 |
EPC2LC20NUBAF48 Overview
A configuration device is a non-volatile serial PROM that streams the FPGA's bitstream through a serial (PS) or JTAG configuration interface at power-up. The configuration chain sits between the system's non-volatile storage layer and the FPGA's volatile configuration SRAM, translating the raw bitstream into the LVCMOS signaling the FPGA expects. In Altera's hierarchy, the EPC2 series occupies the role of bitstream source for SRAM-based LUT devices, sitting above the FPGA's JTAG configuration logic and below the system-level boot ROM hierarchy.
Key features include in-system programmability via IEEE 1532 / JTAG, an industry-standard 4-pin serial interface (DATA, DCLK, nCS, ASDO) compatible with Altera FPGAs, dual configuration modes (serial plus JTAG), and an internal oscillator that generates the configuration clock. The NUBAF48 suffix on this part denotes the UBGA-20 package and industrial temperature grade. Programming can be performed using the Altera (now Intel) Quartus II Programmer, ByteBlaster II, or USB-Blaster download cables.
Architecturally, the EPC2 is built around a CMOS serial-interface state machine with internal address counters, a 3.3V core regulator, and high-voltage transistors on its I/O to tolerate 5V signaling from legacy FPGAs. Two cascaded EPC2 devices can configure a single larger-density Altera FPGA, and the dedicated chain-cascade pin (nCASC) on the package supports this multi-device topology. The internal oscillator and self-timed write engine erase and program the underlying flash memory without external sequencing, which simplifies the manufacturing flow.
Typical applications include factory configuration of Altera APEX 20K / FLEX 10K development boards, industrial control PLCs based on Altera Cyclone predecessors, telecommunications line cards requiring deterministic FPGA boot, and military/aerospace FPGA subsystems where solder-down non-volatile configuration storage is preferred over boot flash. Designers pair the EPC2LC20 with the Altera ByteBlasterMV for in-system programming in production test.
When designing with this device, note that the 'L' suffix denotes the 3.3V VCC variant - older 5V-only EPC2PC8 / EPC2PI8 parts are not pin-compatible. Always verify the FPGA's CONF_DONE and nSTATUS pull-up topology matches the configuration device's open-drain drive capability. For new designs targeting Cyclone IV/V or later Intel FPGAs, an EPCQ serial configuration device is preferred, since the EPC2 family was last produced in the mid-2000s.
Drop-in alternatives for EPC2LC20NUBAF48 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2LC20NUBAF48 (same form factor and footprint) — differing in Memory Type, Package, Supported FPGA Families, Cascade Support, Configuration Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC2LC20N
✅ Drop-In✓ In Stock
$7.4 / Unit
View Datasheet →EPC2LC20NA
✅ Drop-In✓ In Stock
$5.5 / Unit
View Datasheet →EPC2LC20
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EPC2LC20-W
✅ Drop-In📋 Reference alternative (not in catalog)
EPC2LC20-V
✅ Drop-In✓ In Stock
$9.45 / Unit
View Datasheet →EPC1LC20
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EPC2LC20NUBAF48 Maximum Ratings & Electrical Characteristics
| Memory Type | Non-volatile flash configuration PROM |
| Memory Density | 2 Mbit (2,097,152 bits) |
| Core Supply Voltage (VCC) | 3.3 V (low-voltage 'L' variant) |
| I/O Logic Levels | 3.3 V LVCMOS (5V-tolerant inputs) |
| Configuration Interface | Altera serial (DATA, DCLK, nCS, ASDO) |
| JTAG / ISP Support | IEEE 1532 / JTAG in-system programming |
| Cascade Support | Yes - dedicated nCASC pin for 2-device chains |
| Programming Voltage | Internal 3.3V generation, no external VPP |
| FPGA Compatibility | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 |
| Package | 20-pin Ultra FineLine BGA (UBGA, NU suffix) |
| Operating Temperature | -40C to +85C (industrial) |
| Configuration Clock | Internal oscillator (DCLK output to FPGA) |
| Programming Tools | Quartus II Programmer, ByteBlaster II, USB-Blaster |
EPC2LC20NUBAF48 Pin Configuration
| Pin A1 | GND — Ground |
| Pin A2 | DATA — Configuration data output to FPGA |
| Pin A3 | DCLK — Configuration clock output to FPGA |
| Pin A4 | nCS — Chip select (active low) from FPGA |
| Pin A5 | ASDO — Serial data output (programming) |
| Pin B1 | VCC — 3.3V core supply |
| Pin B2 | nCASC — Cascade output to slave EPC2 |
| Pin B3 | nSTATUS — Configuration status to FPGA |
| Pin B4 | CONF_DONE — Configuration done signal to FPGA |
| Pin B5 | OE — Output enable (active low) |
| Pin C1 | TCK — JTAG test clock |
| Pin C2 | TMS — JTAG test mode select |
| Pin C3 | TDI — JTAG test data in |
| Pin C4 | TDO — JTAG test data out |
| Pin C5 | GND — Ground |
| Pin D1 | VCC — 3.3V core supply |
| Pin D2 | NC — Not connected |
| Pin D3 | NC — Not connected |
| Pin D4 | nINIT_CONF — Initiate configuration (active low) |
| Pin D5 | GND — Ground |
Typical Applications
EPC2LC20NUBAF48 is suitable for 6 applications: APEX 20K / APEX II FPGA Configuration, FLEX 10K / ACEX 1K Board Boot, In-System Programming via JTAG (IEEE 1532), Cascaded Configuration of High-Density Altera FPGAs, Legacy Industrial Control PLCs, Aerospace & Defense FPGA Subsystems.
APEX 20K / APEX II FPGA Configuration
The EPC2LC20NUBAF48 is the canonical configuration device for Altera's APEX 20K and APEX II SRAM-based LUT FPGAs, providing 2 Mbit of non-volatile bitstream storage that the FPGA loads over the serial configuration interface at every power-up. Designers place it on the configuration bus alongside the 4-wire DATA/DCLK/nCS/ASDO chain from the FPGA, and use the nCASC pin to configure larger APEX 20K devices (such as the EP20K400) by cascading a second EPC2. The 3.3V core and 5V-tolerant I/O simplify mixed-voltage board designs where the FPGA core runs at 1.8V-2.5V but legacy peripherals remain at 5V.
Recommended
FLEX 10K / ACEX 1K Board Boot
The EPC2LC20NUBAF48 configures FLEX 10K, FLEX 10KA, and ACEX 1K family FPGAs over Altera's PS (passive serial) configuration mode, streaming the bitstream synchronously on the rising edge of the internal DCLK oscillator. Its 2 Mbit density covers the largest FLEX 10K devices (such as EPF10K250A) in a single device, eliminating the need for an external boot PROM. The internal oscillator means no external configuration clock is required, simplifying PCB layout and reducing BOM cost in legacy Altera-based industrial control boards.
Recommended
In-System Programming via JTAG (IEEE 1532)
The EPC2LC20NUBAF48 supports IEEE 1532 JTAG in-system programming, allowing firmware updates without removing the part from the board - critical for factory programming and field-upgrade scenarios in telecommunications and aerospace FPGA subsystems. A USB-Blaster or ByteBlasterMV cable drives TDI/TDO/TCK/TMS into the JTAG chain, and the Quartus II Programmer issues EPC2-specific BSDL instructions to erase, blank-check, program, and verify the 2 Mbit flash array. Because the EPC2 sits between the JTAG header and the FPGA in the chain, JTAG can also reach the configured FPGA concurrently.
Recommended
Cascaded Configuration of High-Density Altera FPGAs
For Altera FPGAs whose bitstream exceeds 2 Mbit (such as the APEX 20K1000E or APEX II EP2A70), two EPC2LC20NUBAF48 devices can be cascaded via the nCASC pin, with the master device's nCASC driving the slave's nCS to extend the addressable storage to 4 Mbit. This dual-PROM topology lets a single reference design scale across multiple FPGA densities without redesigning the configuration hardware. The 3.3V VCC and internal oscillator simplify the layout when both EPC2s sit on opposite sides of the FPGA BGA.
Recommended
Legacy Industrial Control PLCs
Long-life industrial control PLCs and SCADA remote-terminal units (RTUs) that were designed around Altera APEX 20K or FLEX 10K FPGAs in the late 1990s and early 2000s still use the EPC2LC20NUBAF48 as their solder-down configuration storage, where field serviceability is less critical than deterministic boot from non-volatile memory. The -40C to +85C industrial temperature grade allows operation in unheated outdoor cabinets, and the BGA package is robust against vibration in motor-drive and substation applications where DIP parts would fail mechanically.
Recommended
Aerospace & Defense FPGA Subsystems
Defense and aerospace programs with long field-deployment lifetimes (15-25 years) continue to specify the EPC2LC20NUBAF48 in MIL-STD-454-compliant boards because the solder-down UBGA-20 BGA provides better mechanical reliability than socketed boot PROMs, and the part's deterministic in-system programming flow supports factory reprogramming without de-lidding hermetic packages. The 3.3V core reduces inrush current during power-up compared with 5V-only predecessors, which is critical for power-sequenced avionics LRUs. Obsolescence planning typically stocks 5-7 years of EPC2 supply at provisioning time.
Recommended
Recommended Products Summary
Engineering reference data for EPC2LC20NUBAF48 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2LC20NA | EPC2LC20 | EPC2LC20-W | EPC2LC20-V | EPC1LC20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 20-pin UBGA (NU suffix) | 20-pin UBGA - same | 20-pin UBGA - same | 20-pin UBGA - same | 20-pin UBGA - same | 20-pin UBGA - same | 20-pin UBGA - same |
| Memory Density | 2 Mbit | 2 Mbit | 2 Mbit | 2 Mbit | 2 Mbit | 2 Mbit | 1 Mbit (-50%) |
| Core Voltage (VCC) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| JTAG / ISP Support | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) |
| Cascade Support (nCASC) | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 5V-tolerant I/O inputs on a 3.3V core (vs EPC2PC8)
- 2-Mbit density vs. 1-Mbit predecessor (vs EPC1LC20)
- JTAG IEEE 1532 in-system programmability (vs EPC2LI20)
Design Notes
Place the EPC2LC20NUBAF48 as close as possible to the Altera FPGA's configuration pins (DATA, DCLK, nCS, nSTATUS, CONF_DONE) to minimize trace length and ringing on the DCLK signal - the configuration interface runs at the internal oscillator frequency (typically tens of MHz) and long stubs cause reflections that manifest as intermittent configuration failures. Add a 0.1uF decoupling capacitor on each VCC pin (B1 and D1) placed within 3 mm of the BGA ball, plus a 10uF bulk capacitor on the 3.3V rail within 25 mm. Keep the JTAG chain (TDI/TDO/TCK/TMS) traces impedance-controlled at 50 ohms if the chain exceeds 50 mm.
Do not confuse the 3.3V EPC2LC20 (NU suffix, UBGA-20) with the 5V EPC2PC8/EPC2PI8 (PDIP-8/SOIC-8). Although the datasheet says both support 5V-tolerant inputs, the EPC2LC20 outputs 3.3V LVCMOS logic which may not meet Vih on 5V-only FPGAs. Verify the target FPGA's CONF_DONE/nSTATUS Vil/Vih before substituting the L-variant for a P-variant on existing 5V boards. Also, never cascade an EPC2LC20 with an EPC2PC8 because the nCASC signaling is incompatible between VCC domains.
When designing the JTAG chain for in-system programming, place the EPC2LC20NUBAF48 between the JTAG header and the FPGA in the chain (TDI -> EPC2-TDI -> EPC2-TDO -> FPGA-TDI -> ...), with 4.7 kohm pull-ups on TCK, TMS, and TDI to VCCIO. The nCASC output of a master EPC2 should be wired to the nCS of a slave EPC2 for cascaded configurations - never leave nCASC floating because it acts as an open-drain output. For multi-FPGA chains, use a JTAG chain fan-out buffer (such as an SN74LVTH125) if the total TCK/TMS loading exceeds 4 devices.
The EPC2LC20NUBAF48 UBGA-20 BGA package has a modest thermal resistance (theta_JA approximately 50 C/W on a 4-layer JEDEC test board), but during in-system programming the device draws elevated peak current for erase/program pulses - up to ~50 mA on VCC versus ~10 mA in standby. Ensure the 3.3V regulator can supply this inrush plus the FPGA's configuration current without sagging below 3.0V, otherwise ISP operations will fail with verify errors. Add at least 100uF of bulk capacitance near the EPC2 for ISP programming margin.
Compliance Information
RoHS, REACH, lead-free, halogen-free and conflict-minerals status could not be confirmed from the verified web data on 2026-09-11; the EPC2LC20 family was originally released before the 2006 RoHS deadline so many lots are non-RoHS - request compliance certificates from brokers when required. AEC-Q100 not applicable since the part is an industrial/storage-class device, not an automotive-qualified IC.
