EPC2T132N - 1.6Mb Config Memory 32-TQFP | Altera (Intel FPGA)
MPN: EPC2T132N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.5 | $9,750.00 |
| 1,000 | $17.8 | $17,800.00 |
EPC2T132N Overview
A serial configuration device is a non-volatile memory IC used to load the configuration bitstream of SRAM-based FPGAs at power-up, since SRAM cells lose their configuration when power is removed. The EPC2 family stores the FPGA's configuration image in flash and streams it serially via the FPGA's dedicated configuration pins (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE). Compared to older EPC1 devices, EPC2 adds in-system programmability, faster 10 MHz clock support, and a denser 1.6 Mbit capacity suitable for larger FPGA bitstreams.
Key features include 1.6 Mbit flash storage, 10 MHz maximum serial clock frequency, in-system programmability via JTAG, 3.3 V core supply, industrial -40C to +85C operating temperature range, and 100,000 program/erase endurance cycles per sector. The device supports multi-device configuration chains for loading multiple FPGAs from a single flash device, with a daisy-chain topology that minimizes board space.
The EPC2T132N uses a 32-pin TQFP (T132) package and is positioned as a legacy configuration device for industrial, telecommunications, and embedded computing applications. Compared to newer EPCQ or EPCS series, EPC2 uses a 4-wire JTAG interface instead of SPI, and a different serial protocol (not SPI-compatible), so it cannot directly replace EPCS parts on a Cyclone V or newer Stratix board.
Typical applications include industrial control boards using legacy FPGAs, military/aerospace retrofits, telecommunications line cards, and embedded computing platforms where Cyclone or Stratix designs require a non-volatile configuration source. The device is also used for prototype development where reconfiguration is needed during firmware iteration.
When designing with EPC2T132N, ensure the JTAG chain includes proper TCK, TMS, TDI, TDO pull-ups and that nCONFIG and nSTATUS lines are properly terminated per the datasheet. The device requires a 10 MHz or slower DCLK from the FPGA; faster clocks are not supported on EPC2 family.
This page synthesizes Altera datasheet specifications, distributor stock data, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPC2T132N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2T132N (same form factor and footprint) β differing in Interface, Package, Supply Voltage, Memory Type, Supported FPGA Families.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2LC20N
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC2T132
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPC2-TI32N
β Drop-Inβ In Stock
$11.5 / Unit
View Datasheet βEPC2-TI32
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.75 / Unit
View Datasheet βEPC2LC22N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.75 / Unit
View Datasheet βEPC2LS20U
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$4.25 / Unit
View Datasheet βEPC2T132N Maximum Ratings & Electrical Characteristics
| Memory Type | Flash (NOR, serial configuration) |
| Memory Capacity | 1.6 Mbit (2 Mbit raw, 1.6 Mbit usable) |
| Serial Clock Frequency | 10 MHz maximum |
| Interface | Altera serial configuration (4-wire JTAG for ISP) |
| Supply Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (industrial) |
| Package | TQFP-32 (T132) |
| Mounting Type | Surface Mount |
| Program/Erase Endurance | 100,000 cycles per sector |
| Data Retention | 20 years minimum |
| In-System Programmable | Yes (IEEE 1149.1 JTAG) |
| Configuration Compatibility | APEX II, APEX 20K, ACEX 1K, FLEX 10K/10KE/6000, Cyclone, Stratix, Mercury |
| Multi-Device Daisy Chain | Yes (supported) |
EPC2T132N Pin Configuration
| Pin 1 | VCC β 3.3 V power supply |
| Pin 2 | GND β Ground |
| Pin 3 | DATA β Serial data output to FPGA |
| Pin 4 | DCLK β Configuration clock input from FPGA |
| Pin 5 | nCONFIG β Configuration control (active low) |
| Pin 6 | nSTATUS β Configuration status (active low) |
| Pin 7 | CONF_DONE β Configuration complete signal |
| Pin 8 | TCK β JTAG test clock |
| Pin 9 | TMS β JTAG test mode select |
| Pin 10 | TDI β JTAG test data input |
| Pin 11 | TDO β JTAG test data output |
| Pin 12 | nCE β Chip enable (active low) |
| Pin 13 | nCS β Chip select (active low) |
| Pin 14 | OE β Output enable |
| Pin 15 | RESET β Reset input |
| Pin 16 | VPP β Programming voltage supply |
| Pin 17 | WP β Write protect |
| Pin 18 | A0 β Address line 0 |
| Pin 19 | A1 β Address line 1 |
| Pin 20 | A2 β Address line 2 |
| Pin 21 | A3 β Address line 3 |
| Pin 22 | GND β Ground |
| Pin 23 | VCC β 3.3 V power supply |
| Pin 24 | NC β Not connected |
| Pin 25 | NC β Not connected |
| Pin 26 | NC β Not connected |
| Pin 27 | NC β Not connected |
| Pin 28 | NC β Not connected |
| Pin 29 | NC β Not connected |
| Pin 30 | GND β Ground |
| Pin 31 | VCC β 3.3 V power supply |
| Pin 32 | VCC β 3.3 V power supply |
Typical Applications
EPC2T132N is suitable for 6 applications: Legacy Altera FPGA Configuration, Industrial Control Boards, Telecommunications Line Cards, Military/Aerospace Retrofit Programs, Embedded Computing Platforms, Prototype Development and Debug.
Legacy Altera FPGA Configuration
The EPC2T132N stores 1.6 Mbit of configuration bitstream in flash, matching the capacity required by legacy Altera FPGAs such as Cyclone EP1C12/EP1C20, Stratix EP1S10/EP1S25, APEX 20K, and FLEX 10KE devices. At power-up, the FPGA acts as configuration master and clocks the bitstream from EPC2T132N via the serial DATA/DCLK pins. The 10 MHz DCLK limit on EPC2 matches the configuration speed requirements of these families, making EPC2T132N the canonical configuration source. For new Cyclone IV/V or Stratix V designs, EPCS or EPCQ parts are required instead.
Recommended
Industrial Control Boards
Industrial control boards using legacy Altera FPGAs rely on EPC2T132N for non-volatile configuration storage because flash memory survives power cycles, unlike the SRAM cells inside the FPGA itself. The -40C to +85C industrial temperature range ensures the configuration bitstream remains valid in factory floor environments. JTAG-based in-system programmability allows field updates to the configuration without removing the IC from the board, simplifying firmware upgrades and reducing downtime. The 100,000 program/erase cycle endurance supports frequent design iteration during product development and field tuning.
Recommended
Telecommunications Line Cards
Telecommunications line cards from the early 2000s typically use APEX 20K or FLEX 10KE FPGAs with EPC2 family configuration devices. The EPC2T132N's 1.6 Mbit capacity fits the typical 600K-1.5M gate bitstreams common in telecom DSP, TDM, and ATM designs. Multi-device daisy-chain support allows a single EPC2 to configure multiple FPGAs on a line card, reducing board area and BOM cost. The TQFP-132 package provides reliable surface-mount assembly in high-vibration environments such as telecom central offices and roadside cabinets.
Recommended
Military/Aerospace Retrofit Programs
Military and aerospace retrofit programs often maintain legacy Altera FPGA designs where EPC2T132N remains the only supported configuration device for qualification and long-term support. The industrial temperature range and high-reliability flash (20-year data retention, 100K cycle endurance) meet the requirements for avionics, radar, and secure communications applications. Program updates via JTAG allow mission-critical firmware updates in deployed systems without hardware swap-out, supporting lifecycle management for platforms with 20-30 year service lives.
Recommended
Embedded Computing Platforms
Embedded computing platforms based on legacy Altera FPGAs use EPC2T132N as the boot configuration source for RISC soft-cores (Nios I/II), custom DSP pipelines, and PCI/PCI-X interface logic. The 1.6 Mbit capacity fits mid-density Nios II designs with custom peripherals. JTAG ISP enables rapid prototyping and iterative development, where configuration bitstreams change frequently during design verification. The TQFP-132 package supports hand-soldering for low-volume prototypes and low-cost assembly houses.
Recommended
Prototype Development and Debug
FPGA prototype development workflows rely on EPC2T132N for rapid bitstream iteration, where the JTAG ISP enables design changes to be pushed to the configuration flash in seconds without IC removal. Quartus II software writes new configuration data to EPC2T132N via JTAG, the FPGA reboots, and the engineer can immediately test the updated design. This workflow is critical during HDL bring-up, timing closure, and integration testing phases where the bitstream may change dozens of times per day.
Recommended
Recommended Products Summary
Engineering reference data for EPC2T132N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20N | EPC2T132 | EPC2-TI32N |
|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Package | TQFP-132 | TQFP-132 - same | TQFP-132 - same | TQFP-132 - same |
| Memory Capacity | 1.6 Mbit | 1.6 Mbit (same) | 1.6 Mbit (same) | 1.6 Mbit (same) |
| Serial Clock Frequency | 10 MHz | 10 MHz | 10 MHz | 10 MHz |
| In-System Programmable | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Interface Protocol | Altera legacy serial | Altera legacy serial | Altera legacy serial | Altera legacy serial |
| Operating Temperature | -40C to +85C | -40C to +85C | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Same EPC2 family with identical 1.6 Mbit capacity (vs EPC2LC20N)
- Industrial temperature grade available (vs EPC2T132 (commercial grade))
- JTAG-based in-system programmability (vs EPCS16SI16N (older EPCS without JTAG ISP))
Design Notes
The EPC2T132N requires a 3.3 V supply (3.0 V to 3.6 V) with a 0.1 uF decoupling capacitor placed as close as possible to each VCC pin. A bulk 10 uF tantalum or ceramic capacitor is recommended near the IC to handle flash programming current spikes. The VPP pin (if present on the package variant) supplies the programming voltage during JTAG ISP and must be properly decoupled. Power sequencing is not required; the device operates correctly with a simple rail ramp.
Route the JTAG signals (TCK, TMS, TDI, TDO) as short traces with 33 ohm series termination if longer than 50 mm. Add 10 kohm pull-ups on TCK, TMS, TDI, and TDO per the JTAG specification to ensure a defined state when no programmer is attached. The serial configuration pins (DATA, DCLK) should be routed with matched impedance to the FPGA, and should be length-matched if the FPGA is more than 50 mm away from the EPC2.
Do not confuse EPC2T132N with EPCS16SI16N: EPC2 uses Altera legacy serial protocol, while EPCS uses SPI. They are NOT pin-compatible or protocol-compatible. Newer Altera FPGAs (Cyclone III/IV/V, Stratix III/IV/V) require EPCS or EPCQ configuration devices and will not boot from EPC2. For new designs, use EPCQ-A or EPCQ4A compatible with Quartus Prime and modern FPGAs.
Compliance Information
Compliance data not available in verified web sources. The Altera datasheet does not specify RoHS/REACH status for legacy EPC2 family. Contact Altera/Intel FPGA for compliance documentation.
