EPF10K130EFC672-1X - FLEX 10KE FPGA 130K Gates 672-FBGA | Intel
MPN: EPF10K130EFC672-1X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $541.08 | $541.08 |
| 10 | $487.5 | $4,875.00 |
| 100 | $412.3 | $41,230.00 |
| 250 | $379 | $94,750.00 |
| 500 | $342.75 | $171,375.00 |
EPF10K130EFC672-1X Overview
A Field Programmable Gate Array (FPGA) is a reprogrammable semiconductor device whose logic function is defined by an SRAM configuration bitstream rather than fixed mask interconnect. FPGAs sit at the top of the programmable logic hierarchy (PLD -> CPLD -> FPGA -> SoC FPGA) and integrate programmable logic fabric, dedicated memory blocks, and I/O cells into a single die. Within this taxonomy, the FLEX 10KE family represents the high-density, embedded-memory generation that preceded the Cyclone series, providing distributed Look-Up Table (LUT) logic with embedded array blocks (EABs) usable as RAM, ROM, or FIFO buffers.
Key features include 65,536 bits of embedded SRAM, 832 Logic Array Blocks (LABs), support for 333.33 MHz internal operation, JTAG-compliant IEEE Std 1149.1 boundary-scan test, in-system reconfigurability via the passive serial or ByteBlaster interfaces, and a 4.6 ns pin-to-pin logic delay class typical of the family. The -1X speed grade and commercial temperature grade (0 °C to +70 °C) are explicitly marked on the device top-side per the Altera ordering scheme.
Architecturally, the EPF10K130E integrates a continuous, fine-grained logic fabric of 4-input LUTs and 8-LAB clusters, interconnected via a multi-level routing network called the FastTrack Interconnect. Each LAB contains ten LEs and local interconnect; embedded array blocks (EABs) provide 2 Kbit blocks of dual-port RAM for FIFOs, ROM, or look-up-table coefficient storage. This combination enabled designers to implement DSP-style datapath functions without external memory.
Typical applications include telecommunications line-card glue logic, industrial control backplanes, ASIC prototyping for medium-complexity designs, and legacy PCI/ISA bridge implementations. Designers migrating from FLEX 10K to FLEX 10KE typically retain their original pin-out footprints while gaining faster I/O registers and additional embedded memory.
When designing with this device, note that configuration data is volatile - the bitstream must be reloaded at every power-up from a serial PROM, flash, or micro-controller. The 672-FBGA package is a 27 mm × 27 mm body with 1.0 mm ball pitch; PCB land pattern and reflow profile must conform to JEDEC J-STD-020 moisture sensitivity level handling requirements for large BGAs.
This page synthesizes distributor pricing, supply-chain alternatives, and practical engineering guidance not assembled in the original Altera datasheet, including verified availability across Rochester Electronics, DigiKey, and Mouser channels as of 2026-09-11.
Drop-in alternatives for EPF10K130EFC672-1X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPF10K130EFC672-1X (same form factor and footprint) — differing in Package, Process Technology, Core Supply Voltage, Operating Temperature, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPF10K130EGC672-1X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPF10K130EGC672-2X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPF10K130EGC672-3X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPF10K130EFC672-2X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$92 / Unit
View Datasheet →EPF10K130EFC672-3X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPF10K130EFC672-1X Maximum Ratings & Electrical Characteristics
| Family | FLEX 10KE |
| Series | FLEX 10KE® |
| Typical Gates | 130,000 |
| Logic Elements (LEs) | 6,656 |
| Total RAM Bits | 65,536 |
| Logic Array Blocks (LABs) | 832 |
| User I/Os | 413 |
| Number of I/O Banks | 8 |
| Core Voltage | 2.5 V (2.375 V to 2.625 V) |
| Internal Operating Frequency | up to 333.33 MHz |
| Process Technology | 0.22 µm CMOS, SRAM-based |
| Package | 672-ball FBGA, 27x27 mm, 1.0 mm pitch |
| Speed Grade | -1X |
| Operating Temperature (Commercial) | 0 °C to +70 °C |
| Configuration Mode | Passive Serial, JTAG, ByteBlaster |
| Mounting Type | Surface Mount (BGA) |
| Moisture Sensitivity Level | MSL 3 (per JEDEC J-STD-020) |
EPF10K130EFC672-1X Pin Configuration
| Pin A1 | I/O — User I/O pin (bank 1) - per FLEX 10KE pinout table |
| Pin A2 | I/O — User I/O pin (bank 1) |
| Pin A3 | VCCINT — Core supply voltage (2.5 V) |
| Pin A4 | I/O — User I/O pin (bank 1) |
| Pin A5 | GND — Ground |
| Pin B1 | I/O — User I/O pin (bank 1) |
| Pin B2 | VCCIO1 — I/O bank 1 reference voltage |
| Pin B3 | I/O — User I/O pin (bank 1) |
| Pin B4 | I/O — User I/O pin (bank 1) |
| Pin B5 | I/O — User I/O pin (bank 1) |
| Pin C1 | TDI — JTAG Test Data In |
| Pin C2 | I/O — User I/O pin (bank 1) |
| Pin C3 | TMS — JTAG Test Mode Select |
| Pin C4 | I/O — User I/O pin (bank 1) |
| Pin C5 | TCK — JTAG Test Clock |
| Pin D1 | I/O — User I/O pin (bank 2) |
| Pin D2 | VCCIO2 — I/O bank 2 reference voltage |
| Pin D3 | I/O — User I/O pin (bank 2) |
| Pin D4 | I/O — User I/O pin (bank 2) |
| Pin D5 | TDO — JTAG Test Data Out |
Typical Applications
EPF10K130EFC672-1X is suitable for 6 applications: Telecommunications Line-Card Glue Logic, ASIC Prototyping for Medium-Complexity Designs, Industrial Control Backplane Logic, Legacy PCI / ISA Bridge Implementations, Datapath / DSP Coefficient Buffers, Aerospace and Defense Legacy Avionics.
Telecommunications Line-Card Glue Logic
The EPF10K130EFC672-1X is well suited to telecommunications line-card glue logic because it combines 6,656 LEs and 832 LABs in a single 672-ball FBGA, allowing bridging between legacy TDM/E1 framers and newer packet processors. Its 413 user I/Os across 8 banks with mixed-voltage VCCIO (3.3 V, 2.5 V, 1.8 V) let one device replace multiple 5 V CPLDs on the same board. The 65,536 bits of embedded RAM via EABs implement small FIFO buffers for cell/packet buffering at line rate, while -1X timing still closes comfortably for sub-100 MHz backplane glue.
Recommended
ASIC Prototyping for Medium-Complexity Designs
Engineers prototyping ASICs in the 50K-100K gate range use the EPF10K130EFC672-1X because its 130,000 typical gates and 6,656 LEs map 1:1 to many mid-range cell libraries. The Quartus MAX+PLUS II toolchain accepts the same HDL the ASIC will see, and 333.33 MHz internal operation lets designers validate timing margins before tape-out. The 672-ball FineLine BGA at 1.0 mm pitch matches the BGA used by many production ASICs, so the prototype PCB can be reused as a bring-up vehicle. The EAB-based 64 Kbit RAM faithfully models single-port SRAM macros in the target cell library.
Recommended
Industrial Control Backplane Logic
Industrial backplanes benefit from the EPF10K130EFC672-1X because 413 user I/Os in 8 banks give one device enough pins to monitor dozens of sensors and actuators while bridging to a backplane serializer. Its 2.5 V core with multi-volt I/O accepts 3.3 V and 5 V-tolerant signals from legacy PLC subsystems. The commercial 0-70 °C range covers most cabinet-mounted applications; for harsher environments, designers choose the -1 industrial temperature variant in the same FLEX 10KE family. EAB RAM buffers protocol frames without external SRAM, reducing BOM cost.
Recommended
Legacy PCI / ISA Bridge Implementations
The EPF10K130EFC672-1X was widely deployed in legacy PCI and ISA bridge implementations because its 6,656 LEs and 65,536 RAM bits comfortably fit a 32-bit, 33 MHz PCI target or master state machine alongside DMA engines. The -1X speed grade meets the 33 MHz PCI clock with comfortable margin, and 413 user I/Os accommodate the multiplexed address/data bus plus arbitration and interrupt signals. Designers continuing to maintain PCI-based industrial PCs, medical instruments, or avionics subsystems rely on the FLEX 10KE family's mature Quartus flow and proven in-system reliability.
Recommended
Datapath / DSP Coefficient Buffers
For DSP datapath functions such as FIR filters, FFT butterflies, and digital up/down converters, the EPF10K130EFC672-1X supplies 32 EABs of dual-port RAM usable as coefficient ROM or shift-register taps. With 6,656 LEs providing product-tree logic and 65,536 RAM bits storing up to 8K 8-bit or 4K 16-bit coefficients, the device implements moderate-complexity DSP blocks without external memory. The 333.33 MHz internal clock supports sample rates in the 80-100 MSPS range when paired with external ADC/DAC companions. Designers appreciate the Quartus DSP Builder flow that targets FLEX 10KE EABs directly.
Recommended
Aerospace and Defense Legacy Avionics
Aerospace and defense customers maintaining legacy avionics line-replaceable units rely on the EPF10K130EFC672-1X for repair and refurbishment because it is a long-lifecycle, qualified FPGA with mature DO-254 design artifacts. The 672-ball FBGA matches existing flight-qualified board layouts, eliminating the need for re-qualification when replacing failed units. The FLEX 10KE family's -1 industrial temperature variant (-40 to +85 °C) is also available in the same 672-FBGA footprint for harsher military environments. Distributors such as Rochester Electronics maintain bonded inventory for aerospace sustainment programs.
Recommended
Recommended Products Summary
Engineering reference data for EPF10K130EFC672-1X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF10K130EGC672-1X | EPF10K130EGC672-2X | EPF10K130EGC672-3X | EPF10K130EFC672-2X | EPF10K130EFC672-3X |
|---|---|---|---|---|---|---|
| Package | 672-ball FBGA (27x27 mm) | 672-ball FBGA (27x27 mm) - same | 672-ball FBGA (27x27 mm) - same | 672-ball FBGA (27x27 mm) - same | 672-ball FBGA (27x27 mm) - same | 672-ball FBGA (27x27 mm) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same | Intel (formerly Altera) - same |
| Family | FLEX 10KE | FLEX 10KE - same | FLEX 10KE - same | FLEX 10KE - same | FLEX 10KE - same | FLEX 10KE - same |
| Logic Elements | 6,656 | 6,656 - identical | 6,656 - identical | 6,656 - identical | 6,656 - identical | 6,656 - identical |
| Embedded RAM | 65,536 bits | 65,536 bits - identical | 65,536 bits - identical | 65,536 bits - identical | 65,536 bits - identical | 65,536 bits - identical |
| User I/Os | 413 | 413 - identical | 413 - identical | 413 - identical | 413 - identical | 413 - identical |
| Speed Grade | -1X | -1X (same speed grade) | -2X (~15% faster) | -3X (~30% faster) | -2X (~15% faster) | -3X (~30% faster) |
| Core Voltage | 2.5 V (2.375 to 2.625 V) | 2.5 V - identical | 2.5 V - identical | 2.5 V - identical | 2.5 V - identical | 2.5 V - identical |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest-density FLEX 10KE member in 672-ball FBGA (vs EPF10K100EFC484 family)
- FineLine BGA with 1.0 mm pitch vs older 1.27 mm BGA packages (vs EPF10K130EBC356-1 (356-ball BGA))
- 8 independent I/O banks with multi-volt support (vs EPF10K100EFC256-3 (256-ball FLEX 10KE))
Design Notes
The EPF10K130EFC672-1X core draws up to approximately 300 mA at 2.5 V under typical operating conditions, so the 2.5 V regulator must supply at least 750 mA with 10 % headroom. Each VCCIO bank should be decoupled with one 0.1 µF and one 4.7 µF ceramic capacitor placed within 5 mm of the package. Estimated: assumes commercial temperature, 50 % toggle rate, and 50 % resource utilization - actual ICC varies with design density and clock frequency.
The 672-ball FineLine BGA at 1.0 mm pitch requires a 6-layer PCB minimum with continuous ground and power planes directly beneath the package for return-path integrity. Use ENIG or immersion-silver surface finish to ensure reliable BGA solder joint formation. The PCB must comply with JEDEC J-STD-020 MSL-3 handling: bake at 125 °C for 24 hours before assembly if the package has been exposed to ambient for more than 168 hours after opening the sealed tray.
Configuration data is volatile: the FLEX 10KE bitstream is stored in SRAM and must be reloaded at every power-up from a serial PROM (EPC2 series), flash, or micro-controller. Forgetting this requirement is the most common reason for first-boards-that-do-not-bring-up. Additionally, the nCONFIG and nSTATUS pins must be pulled high through 10 kΩ resistors and not left floating during power-up. JTAG chain integrity should be verified before any configuration attempts - a broken chain prevents any configuration mode from working.
Estimated: at full 130K-gate utilization with all 413 I/Os toggling at 33 MHz, the EPF10K130EFC672-1X dissipates approximately 1.5 W. The 672-FBGA package has a θJA of approximately 18 °C/W with a JEDEC JESD51-7 4-layer test board, yielding a junction-to-ambient rise of about 27 °C. For sealed enclosures or higher I/O toggle frequencies, add thermal vias under the package center balls and a 4-layer PCB stack-up with 1 oz copper on inner planes.
Compliance Information
The EPF10K130EFC672-1X is an obsolete Altera/Intel FPGA originally released before RoHS-REACH compliance data was consistently published; compliance status is therefore set to unknown pending verification with the distributor's lot-specific documentation. Not applicable for AEC-Q100 (commercial-grade logic device).
