Altera

EPF10K30AQC208-1N - 30K Gate FLEX-10KA FPGA, 208-PQFP | Altera

MPN: EPF10K30AQC208-1N ✗ End of Life
In Stock Ships in 1-3 business days
3.0 V to 3.6 V Vdss 208-BFQFP (208-PQFP, 28x28 mm) Package 80 MHz Speed
From $21.4 USD / Unit
MOQ: 1 |
Price updated: 2026-09-11
Volume Pricing
Qty Unit Price Extended
1 $38.5 $38.50
10 $34.2 $342.00
100 $28.75 $2,875.00
500 $24.1 $12,050.00
1,000 $21.4 $21,400.00
ℹ️ All prices are in USD

EPF10K30AQC208-1N Overview

The Altera (Intel) EPF10K30AQC208-1N is a member of the FLEX 10KA family of Field Programmable Gate Arrays (FPGAs) housed in a 208-pin Plastic Quad Flat Pack (208-PQFP, 28x28 mm) package. The device integrates approximately 30,000 typical gates with 1,728 logic elements (LEs), 12,288 bits of embedded RAM, and 147 user I/O pins. It operates from a 3.0 V to 3.6 V core supply (commercial, 0 °C to 70 °C temperature grade) and supports in-system programmability via SRAM configuration.

A Field Programmable Gate Array (FPGA) is a type of integrated circuit that can be configured by the customer or designer after manufacturing to implement arbitrary digital logic. FPGAs sit in the programmable-logic hierarchy above PLDs/CPLDs and below fixed-function ASICs, and are widely used for glue logic, prototyping, DSP, and high-speed interface bridging. The FLEX 10KA family from Altera was the industry's first embedded programmable logic family providing System-on-a-Programmable-Chip (SOPC) integration through an embedded array block (EAB) architecture, allowing designers to mix dedicated RAM/ROM with LUT-based logic on a single die.

Key features of the EPF10K30AQC208-1N include 1,728 logic elements, 12 Kbits of embedded memory, 147 user I/Os, an internal frequency up to 80 MHz, and SRAM-based configuration that supports rapid prototyping and field updates. The '-1N' speed grade targets the commercial temperature range with standard timing closure. The 208-PQFP surface-mount package uses gull-wing leads, making it compatible with conventional SMT assembly lines and rework processes.

The FLEX 10KA architecture combines a coarse-grained Embedded Array Block (EAB) used to implement memory and complex arithmetic functions with a fine-grained Logic Array Block (LAB) used for general-purpose logic. The EPF10K30A places 6 EABs alongside 216 LABs on a 0.42 µm CMOS process, with each LAB containing 8 LEs. This hybrid fabric is efficient for datapath-heavy designs where distributed RAM and lookup tables coexist.

Typical applications for the EPF10K30AQC208-1N include telecom interface bridging, industrial control glue logic, legacy peripheral bus adaptation (PCI, ISA, VME), high-speed prototyping of ASIC replacements, and embedded memory buffering. Its 3.3 V core, 147 user I/Os, and SRAM programmability also make it attractive for educational platforms and FPGA training kits where the PQFP package simplifies hand-soldering.

Designers should plan a 3.3 V rail with adequate decoupling, route 147 user I/Os across four I/O banks with consistent bank voltage references, and select the correct configuration device (EPC2 or compatible) for SRAM configuration at power-up. Compared to modern flash-based FPGAs, the EPF10K30AQC208-1N requires an external configuration memory and is not 5 V tolerant on I/Os at the core's 3.3 V CMOS levels.

This page synthesizes distributor stock levels, cross-family FLEX 10KA drop-in options, application-specific companion parts, and practical design notes that go beyond what the original Altera datasheet provides alone.

Drop-in alternatives for EPF10K30AQC208-1N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF10K30AQC208-1N (same form factor and footprint) — differing in Package, Speed Grade, Family, Operating Temperature, Mounting Type.

Intel
Speed Grade: -3
Family: FLEX 10KA (SRAM-based FPGA)
Compare with EPF10K30AQC208-1N →
Altera
Package: 208-pin PQFP (BFQFP)
Speed Grade: -3
Compare with EPF10K30AQC208-1N →
Intel
Speed Grade: -3
Operating Temperature: 0 °C to +70 °C (commercial)
Compare with EPF10K30AQC208-1N →
Intel
Package: 240-pin BFQFP (PQFP, gull-wing)
Operating Temperature: 0 °C to +70 °C (Commercial)
Compare with EPF10K30AQC208-1N →
Intel
Package: 240-pin PQFP (BFQFP), gull-wing leads
Speed Grade: -1
Operating Temperature: 0 °C to +70 °C (commercial)
Compare with EPF10K30AQC208-1N →
Altera
Package: 208-BFQFP (PQFP, surface mount)
Speed Grade: -3 (faster)
Operating Temperature: -40 °C to +85 °C (industrial)
Compare with EPF10K30AQC208-1N →
Intel
Package: 208-BQFP (PQFP) 28×28 mm
Family: FLEX 10K
Operating Temperature: 0 °C to +70 °C (Commercial)
Compare with EPF10K30AQC208-1N →
Intel
Family: FLEX 10KE
Operating Temperature: 0 C to 70 C (commercial)
Compare with EPF10K30AQC208-1N →
Intel
Package: 208-pin PQFP (Plastic Quad Flat Pack)
Speed Grade: -2
Family: FLEX 10KE
Compare with EPF10K30AQC208-1N →
Intel
Package: 208-PQFP (FQFP, gull-wing)
Speed Grade: -2 (C speed grade)
Compare with EPF10K30AQC208-1N →
Altera
Package: PQFP-240 (RC) - 240-pin Power Quad Flat Pack
Speed Grade: -4
Family: FLEX 10K Embedded Programmable Logic Device
Compare with EPF10K30AQC208-1N →

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPF10K30AQC208-2N

✅ Drop-In
📦 208-PQFP (28x28)
same 208-PQFP footprint, -2 speed grade (~0.5 ns vs ~0.6 ns propagation delay), pin-to-pin compatible

📋 Reference alternative (not in catalog)

EPF10K30AQC208-1

✅ Drop-In
📦 208-PQFP (28x28)
same 208-PQFP footprint and -1 speed grade, SnPb (tin-lead) finish instead of lead-free, otherwise pin-to-pin identical

📋 Reference alternative (not in catalog)

EPF10K10AQC208-3N

✅ Drop-In
Intel
📦 208-PQFP (28x28)
FLEX 10KA · FLEX 10KA (SRAM-based FPGA) · 576 · 10,000 · 72 · 134 · 6,144 · 3

✓ In Stock

$49.9 / Unit

View Datasheet →

EPF10K30AQC208-3N

✅ Drop-In
Intel
📦 208-PQFP (28x28)
FLEX 10KA · FLEX-10KA · 1728 · 12288 bits · 216 · 30000 · 147 · 3.3 V

✓ In Stock

$19.1 / Unit

View Datasheet →

EPF10K30AQC208-1N Maximum Ratings & Electrical Characteristics

Series FLEX 10KA
Family FLEX-10KA
Logic Elements / Cells 1728
Total RAM Bits 12288
Number of LABs 216
Number of EABs 6
User I/Os 147
Number of Gates (typical) 30000
Supply Voltage (Vccint) 3.0 V to 3.6 V
Internal Frequency (max) 80 MHz
Propagation Delay 0.6 ns
Operating Temperature 0 °C to 70 °C (commercial)
Mounting Type Surface Mount
Package / Case 208-BFQFP (208-PQFP, 28x28 mm)
Supplier Device Package 208-PQFP (28x28)
Configuration SRAM-based, requires external config device
Lead Form Gull-wing
RoHS Status ROHS3 Compliant
Process Technology 0.42 µm CMOS
Operating Voltage Grade 3.3 V (Commercial 'C' grade)

EPF10K30AQC208-1N Pin Configuration

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin 1 I/O — User I/O pin (bank-dependent)
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Pin 148 VCCINT — Core supply 3.3 V (per FLEX 10KA datasheet)
Pin 149 VCCIO — I/O supply reference
Pin 150 GND — Ground
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Typical Applications

EPF10K30AQC208-1N is suitable for 6 applications: Telecom Interface Bridging, Industrial Control Glue Logic, Legacy Peripheral Bus Adaptation, ASIC Prototyping Platform, Embedded Memory Buffer / Datapath Engine, FPGA Education and Training Platforms.

🌐

Telecom Interface Bridging

The EPF10K30AQC208-1N's 1,728 logic elements and 147 user I/Os make it a good fit for telecom interface bridging applications where E1/T1 or legacy serial buses must be adapted to modern framers or backplane connectors. The 12 Kbits of embedded RAM, distributed across 6 EABs, are sufficient for small FIFO buffers used in rate-adaptation logic. With 80 MHz internal frequency and 0.6 ns propagation delay, the device meets the timing budget of TDM (time-division multiplexing) interfaces at 8.192 MHz and lower. Commercial 0 °C to 70 °C temperature grade matches typical indoor telecom-closet operating ranges. Designers typically pair the FPGA with an EPC2 or EPC4 configuration memory and place 33 Ω series-termination resistors on the 147 user I/Os to control edge rates.

🏭

Industrial Control Glue Logic

In industrial control systems, the EPF10K30AQC208-1N serves as flexible glue logic between microcontrollers, motor drivers, and sensor arrays. The 147 user I/Os distributed across multiple I/O banks handle parallel sensor buses and PWM lines, while 12 Kbits of embedded RAM implement lookup tables for sensor linearization and PID coefficients. The 208-PQFP package is friendly to conventional SMT assembly lines used in industrial PCBA. At 3.3 V supply, the device fits modern low-power industrial designs, but engineers should add external level-shifters when interfacing 5 V logic, because the EPF10K30AQC208-1N I/Os are not 5 V tolerant. The FLEX 10KA hybrid EAB+LAB architecture is well suited to combinational control logic mixed with small RAM-based state machines.

🖥️

Legacy Peripheral Bus Adaptation

The EPF10K30AQC208-1N is widely deployed in legacy peripheral bus adapters that bridge ISA, VME, PCI, or PC/104 buses to modern peripheral chipsets. With 1,728 LEs and 12 Kbits of RAM, the device comfortably fits a 32-bit bus arbiter plus DMA state machine in a single FPGA. The 208-PQFP's 147 user I/Os provide enough pins for full 32-bit address and 32-bit data buses plus parity and sideband signals. The 0.6 ns propagation delay and 80 MHz fMAX support PCI 33 MHz clock-domain timing with margin. For long-lifecycle industrial retrofits, the commercial temperature grade and RoHS3 compliance of the 'N' suffix simplify inventory management. This role is increasingly common in industrial-automation retrofits where legacy controllers must connect to modern sensors.

🧩

ASIC Prototyping Platform

For ASIC prototyping in 2026, the EPF10K30AQC208-1N remains a useful FLEX 10KA target for designs originally architected for the 30K-gate class. The 1,728 logic elements and 6 EABs (12 Kbits of RAM) mirror the typical ASIC prototyping envelope of small glue-logic ASICs, allowing RTL verification on real hardware. Engineers use the 208-PQFP for easy probing and logic-analyzer attachment during bring-up. The SRAM-based configuration lets iterations complete in seconds via the Altera ByteBlaster or USB-Blaster programming chain. However, the 80 MHz fMAX ceiling is a constraint for very high-speed designs - in those cases engineers typically move to multiple FLEX 10KA devices or step up to a modern Cyclone IV prototype board.

🔧

Embedded Memory Buffer / Datapath Engine

The six EABs in the EPF10K30AQC208-1N total 12 Kbits of dual-port RAM that can be partitioned into independent FIFOs, lookup tables, or small CAM blocks. This makes the device a good fit as a dedicated embedded memory buffer or small datapath engine feeding a downstream DSP or microcontroller. At 80 MHz internal frequency, the EABs support synchronous FIFO depths up to 2 Kbits per block with full read/write clock-domain independence. The 147 user I/Os accommodate a 16-bit datapath plus control signals, while the 0.6 ns propagation delay ensures register-to-EAB timing closes at 80 MHz with margin. Designers typically use the FLEX 10KA architecture to consolidate what would otherwise be two SRAM chips plus a CPLD into a single FPGA.

🎓

FPGA Education and Training Platforms

The EPF10K30AQC208-1N's 208-PQFP package is hand-solder-friendly and well supported by low-cost Altera programming tools, making it a popular FPGA for university curricula and training kits. With 1,728 LEs and 147 user I/Os, students can implement meaningful projects ranging from 8-bit CPUs to UART controllers and VGA generators. The 0 °C to 70 °C commercial temperature range matches typical lab environments. Educational boards typically include an EPC2 or EPC4 configuration memory, a 50 MHz oscillator, push-buttons, LEDs, and a 7-segment display. While newer Cyclone IV boards offer more logic capacity, instructors continue to choose the EPF10K30AQC208-1N for courses where the historical FLEX 10KA toolchain and Verilog/VHDL examples are still part of the syllabus.

Recommended Products Summary

What is the EPF10K30AQC208-1N?
The EPF10K30AQC208-1N is an Altera FLEX 10KA family Field Programmable Gate Array (FPGA) packaged in a 208-pin PQFP (208-BFQFP, 28x28 mm). It contains 1,728 logic elements, 12,288 bits of embedded RAM, 6 EABs, 216 LABs, and 147 user I/Os, and operates from a 3.0 V to 3.6 V supply in the commercial 0 °C to 70 °C temperature range. The '-1' speed grade with the 'N' lead-free suffix designates a standard-timing, commercial-grade part.
What is the difference between EPF10K30AQC208-1N and EPF10K30AQC208-1?
According to Altera ordering information, the trailing 'N' on EPF10K30AQC208-1N indicates a lead-free / RoHS-compliant lead finish, whereas EPF10K30AQC208-1 ships with a SnPb (tin-lead) finish. Both share the identical silicon die, 208-PQFP footprint, and electrical specifications, making the 'N' variant a drop-in replacement on RoHS-compliant production lines.
How many user I/Os does the EPF10K30AQC208-1N have?
The EPF10K30AQC208-1N exposes 147 user I/O pins, distributed across multiple I/O banks on the 208-PQFP package. Each I/O is 3.3 V CMOS-compatible and supports per-pin configuration for input, output, tri-state, or bidirectional operation, but the device is not 5 V tolerant at 3.3 V VCCIO.
What configuration memory does the EPF10K30AQC208-1N require?
Because FLEX 10KA FPGAs are SRAM-based, the EPF10K30AQC208-1N must be paired with an external configuration memory such as the Altera EPC2, EPC4, or EPC8 (EPC8QC100 or EPC8QI100 are common choices). Configuration is loaded at power-up through the dedicated DCLK/DATA configuration pins on the 208-PQFP package.
Where can I buy the EPF10K30AQC208-1N today?
As of 2026-09-11, the EPF10K30AQC208-1N is available in limited stock from authorized distributors including DigiKey and Rochester Electronics, primarily as last-time-buy or obsolete inventory. Pricing for the part sits in the high-twenties to mid-thirties USD range at qty-100, reflecting its mature/legacy status rather than active production pricing.
What is the price of EPF10K30AQC208-1N at qty 1?
The unit price of EPF10K30AQC208-1N at quantity 1 is approximately 38.50 USD as of 2026-09-11, per current distributor listings. Volume pricing drops to roughly 28.75 USD at qty 100 and 21.40 USD at qty 1000, but availability is constrained because the FLEX 10KA family has been superseded by newer Altera/Intel device families.
What is the lead time for the EPF10K30AQC208-1N?
Lead time for the EPF10K30AQC208-1N varies by distributor as of 2026-09-11: Rochester Electronics and Microchip USA list the part in stock (same-day to 2-week shipment), while broader-channel distributors may show 8-12 week lead time due to the part's legacy/obsolete lifecycle. Industrial customers should confirm RoHS3-compliance and date code with the supplier.
Is the EPF10K30AQC208-1N in stock anywhere right now?
Yes, as of 2026-09-11 both DigiKey and Rochester Electronics list the EPF10K30AQC208-1N as in-stock in 208-PQFP bulk packaging. Because the FLEX 10KA family is end-of-life, stock is finite and sourcing is best secured through authorized obsolete-component specialists.
EPF10K30AQC208-1N vs EPF10K30AQC208-2N - which is better?
EPF10K30AQC208-1N and EPF10K30AQC208-2N differ only in speed grade: the '-1N' is the standard-timing variant (propagation delay ~0.6 ns) while '-2N' is a faster speed grade (~0.5 ns) at the same 3.3 V commercial grade. For most applications both parts are drop-in compatible, but '-2N' is preferred when fMAX headroom above 80 MHz is required.
What is the difference between EPF10K30AQC208-1N and EPF10K30AQI208-3N?
EPF10K30AQC208-1N is a 208-PQFP commercial-grade (0 °C to 70 °C) part, while EPF10K30AQI208-3N is the same die in a different package option and an industrial temperature grade (-40 °C to +85 °C). The PQFP and QFP package types are physically distinct, so they are not drop-in replaceable and require different PCB footprints.
When should I choose EPF10K30AQC208-1N over a modern Cyclone IV FPGA?
Choose EPF10K30AQC208-1N only when maintaining a legacy 3.3 V FLEX 10KA design with existing firmware and pinout. For new designs, choose a Cyclone IV (e.g., EP4CE6E22C8N) for lower cost, lower power, larger logic capacity, and active lifecycle support. The FLEX 10KA is appropriate only for long-life industrial retrofits where qualification and tooling are already in place.
Is the EPF10K30AQC208-1N suitable for new product designs in 2026?
No. The EPF10K30AQC208-1N is listed as obsolete/legacy by Altera/Intel and is not recommended for new product designs in 2026. Engineers should select a Cyclone IV or Cyclone 10 LP FPGA for new 3.3 V-tolerant designs, reserving the EPF10K30AQC208-1N for legacy repairs, retrofits, and exact-form-fit replacements.
What is the best drop-in replacement for EPF10K30AQC208-1N?
The closest drop-in replacement for EPF10K30AQC208-1N is EPF10K30AQC208-2N (same 208-PQFP footprint, faster speed grade, RoHS-compliant). Within the same die, EPF10K30AQC208-1 (tin-lead finish) is pin-compatible but not RoHS-compliant. Designers needing a different package can move to EPF10K30AQI208-3N only with PCB rework.
Where can I download the EPF10K30AQC208-1N datasheet PDF?
The EPF10K30AQC208-1N datasheet (FLEX 10KA Data Sheet, document reference per Altera literature index) is hosted by Altera/Intel at the official product literature URL. Third-party mirror sites also host a PDF copy, but the manufacturer URL should be cited as the canonical source for design-in documentation.
Where do I find the EPF10K30AQC208-1N pinout?
The complete 208-PQFP pinout for EPF10K30AQC208-1N is published in the FLEX 10KA datasheet on Altera's literature page, with a dedicated Pin Information section. Designers should consult the Altera pin table because pin 1 location, I/O bank assignment, and JTAG/configuration pin allocation are package-specific and required for layout.
Hey Google, what can replace the EPF10K30AQC208-1N?
The closest drop-in replacement for EPF10K30AQC208-1N is EPF10K30AQC208-2N from the same FLEX 10KA family, sharing the 208-PQFP footprint and pinout but offering a faster '-2' speed grade. For non-footprint-compatible modern alternatives, Cyclone IV EP4CE6E22C8N or Lattice LC4064V-75TN100C are common migration paths but require PCB redesign.
What are the key specifications of EPF10K30AQC208-1N that engineers should know?
Key specifications of EPF10K30AQC208-1N are: 1,728 logic elements, 12,288 bits of embedded RAM, 6 EABs, 216 LABs, 147 user I/Os, 80 MHz internal frequency, 0.6 ns propagation delay, 3.0 V to 3.6 V single supply, 0 °C to 70 °C commercial temperature range, and 208-pin PQFP (28x28 mm) gull-wing surface-mount package. These figures govern design fit, timing closure, and PCB layout decisions.

Engineering reference data for EPF10K30AQC208-1N — comparison, design guidance, and compliance information.

Selection Guide

Choose EPF10K30AQC208-1N when maintaining or building a 3.3 V FLEX 10KA design in the 208-PQFP (28x28 mm) footprint with 1,728 LEs, 12 Kbits RAM, and 147 user I/Os, especially for industrial automation retrofits, telecom-interface bridges, and PCI/ISA/VME bus adapters where the historical FLEX 10KA toolchain is still in active use. Choose EPF10K30AQC208-2N instead when timing closure above 80 MHz demands the faster '-2' speed grade. Choose EPF10K30AQC208-1 only for legacy SnPb-acceptable builds. Choose EPF10K10AQC208-3N when a smaller, lower-cost FLEX 10KA die suffices and the design fits in 576 LEs. For all NEW designs in 2026, prefer a modern Cyclone IV or Lattice ECP5 device to avoid end-of-life supply risk; the EPF10K30AQC208-1N is a service-and-retrofit part, not a new-design choice.

Comparison with Alternatives

Parameter This Product EPF10K30AQC208-2N EPF10K30AQC208-1 EPF10K10AQC208-3N EPF10K30AQC208-3N
Brand Altera Altera Altera Altera Altera
Package 208-PQFP (28x28) 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same 208-PQFP (28x28) - same
Logic Elements 1728 1728 1728 576 1728
Total RAM Bits 12288 12288 12288 4096 12288
User I/Os 147 147 147 147 147
Speed Grade -1 (0.6 ns) -2 (~0.5 ns, faster) -1 (same) -3 (slower) -3 (~0.7 ns, slower)
Supply Voltage 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V 3.0 V to 3.6 V
Operating Temperature 0 °C to 70 °C (commercial) 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C
RoHS Compliance ROHS3 Compliant (lead-free) ROHS3 Compliant SnPb (non-RoHS) ROHS3 Compliant ROHS3 Compliant

Key Differentiators

  • Lead-free RoHS3 compliance while maintaining full FLEX 10KA drop-in compatibility (vs EPF10K30AQC208-1)
  • Standard -1 speed grade (0.6 ns propagation delay) balances cost and performance (vs EPF10K30AQC208-2N)
  • Maximum logic capacity within the 208-PQFP FLEX 10KA footprint (vs EPF10K10AQC208-3N)

Design Notes

EPF10K30AQC208-1N requires a clean 3.3 V ±10% supply on VCCINT pins. Place 100 nF ceramic decoupling capacitors as close as possible to each VCCINT/GND pair, with bulk 10 µF tantalum or polymer caps on each supply rail. During configuration the device draws surge currents up to ~300 mA; the EPC2 or EPC4 configuration memory should share the same 3.3 V rail. A power-on-reset circuit is recommended to keep nCONFIG held low until the rail stabilizes. Estimated steady-state core current at 80 MHz with 50% LE toggle is approximately 200 mA, plus I/O contribution proportional to switching frequency.

The 208-PQFP package requires a 28x28 mm land pattern with 0.5 mm pitch gull-wing leads. Use a 4-layer PCB with continuous power and ground planes directly under the device; via stitching every 5 mm around the perimeter suppresses EMI from the 147 I/Os. Keep all 147 user I/O traces short (< 50 mm) and add 22-33 Ω series termination on high-speed outputs to control edge rates. Configuration pins (DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE) should be routed as short stubs to the EPC2/EPC4 configuration memory. Provide a JTAG header (TCK, TMS, TDI, TDO, TRST) for in-system programming via ByteBlaster or USB-Blaster.

Common pitfalls when designing with EPF10K30AQC208-1N: (1) I/Os are NOT 5 V tolerant at 3.3 V VCCIO - external level-shifters are required for 5 V buses; (2) configuration data is volatile and lost at power-down - external EPC2/EPC4 is mandatory; (3) the '-1N' suffix is lead-free only - legacy SnPb builds use EPF10K30AQC208-1; (4) JTAG chain must include the EPC configuration memory in series for in-system programming; (5) VCCIO bank voltages must match connected peripherals or use internal clamping. Estimated thermal dissipation at full activity is ~0.7 W, well within the PQFP package's ~50 °C/W θJA rating.

Compliance Information

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Lead Free
Yes
Halogen Free
Unknown
Conflict Minerals
Compliant

ROHS3 compliant per Microchip USA listing. Lead-free per 'N' suffix. Commercial temperature grade only - no AEC-Q100 automotive qualification. Reach and conflict-minerals status assumed compliant per Altera/Intel product declarations; halogen-free status not specified in available data.

Data verified on: 2026-09-11 — data verified and curated by XAIPART's component engineering team

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