Altera

EPF6024ATC144-14 - FLEX 6000 FPGA, 24K Gates, 144-TQFP | Altera

Name: EPF6024ATC144-14 - FLEX 6000 FPGA, 24K Gates, 144-TQFP | Altera
Brand: Altera
SKU: EPF6024ATC144-14
Price: 17.8 USD
Availability: InStock

MPN: EPF6024ATC144-14 ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss 144-pin TQFP Package -14 (slowest commercial) Speed SRAM (volatile, external ROM required) Memory

From $17.8 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$28.5	$28.50
10	$25.2	$252.00
100	$22.1	$2,210.00
500	$19.5	$9,750.00
1,000	$17.8	$17,800.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EPF6024ATC144-14 Overview

The Altera EPF6024ATC144-14 is a member of the FLEX 6000 family of SRAM-based Field-Programmable Gate Arrays (FPGAs) housed in a 144-pin Thin Quad Flat Pack (TQFP) package. It integrates 24,000 typical gates (logic density), 1,960 logic elements (LEs) organized as 196 Logic Array Blocks (LABs), and 117 user I/O pins, making it a mid-density programmable logic solution for glue logic, bus interfacing, and state-machine-heavy designs in the late-1990s/early-2000s era.

A Field-Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that uses an array of configurable logic blocks (CLBs/LABs), programmable interconnects, and programmable I/O cells to implement arbitrary digital logic. FPGAs sit at the top of the programmable logic hierarchy (PLD -> CPLD -> FPGA) and offer the highest logic density and richest feature set at the cost of higher static power consumption and configuration memory requirements. The FLEX 6000 family uses a look-up-table (LUT)-based LAB architecture with SRAM configuration memory, requiring an external configuration ROM on power-up.

Key features of the EPF6024ATC144-14 include: 1,960 LEs, 196 LABs, 117 user I/O pins, typical operating frequency up to 200 MHz at the -3 speed grade, and 5V-tolerant I/O on a 3.3V core supply. The -14 speed grade denotes the slowest commercial grade, targeting cost-sensitive industrial and consumer applications where clock rates below 100 MHz are acceptable. The 144-pin TQFP package is a plastic surface-mount form factor with 0.5 mm lead pitch and a 22 mm x 22 mm body, designed for standard SMT reflow assembly.

The FLEX 6000 architecture uses a four-input LUT-based logic element, a hierarchical interconnect with FastTrack continuous routing, and embedded memory. The 1960-LE capacity is sufficient for medium-complexity glue logic, peripheral bridges, custom bus controllers, and instrumentation front-ends, but is now considered low-density by modern standards.

Typical applications include industrial motor-control interfaces, telecommunications line cards, custom peripheral bridges in legacy embedded systems, test and measurement backplanes, and ASIC prototyping. The 117 I/O pins support wide parallel buses (16-bit or 18-bit) common in legacy parallel interfaces such as ISA, PC/104, and VME.

When designing with this device, note that the FLEX 6000 family is mature and Intel/Altera recommends the MAX II or Cyclone series for new designs; the EPF6024ATC144-14 remains useful for long-lifecycle products, EOL bridge buys, and existing board repairs. Configuration requires an EPC configuration device or microcontroller-based configuration mode.

This page synthesizes distributor availability, parametric alternatives in the same 144-pin TQFP footprint, and practical lifecycle/design notes not consolidated on the manufacturer product page.

Drop-in alternatives for EPF6024ATC144-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6024ATC144-14 (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, Process Technology, Configuration Memory.

EPF6016ATC144-3

Intel

Package: TQFP-144 (20 x 20 mm)

Speed Grade: -3

Operating Temperature: 0 °C to +85 °C (commercial)