Intel

EPF6016ATC144-3 - FLEX 6000 FPGA, 16K Gates, 1320 Cells | Intel

MPN: EPF6016ATC144-3 ✗ End of Life

In Stock Ships in 1-3 business days

3.3 V Vdss TQFP-144 (20 x 20 mm) Package 142.86 MHz Speed

From $9.85 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.75	$1,375.00
500	$11.4	$5,700.00
1,000	$9.85	$9,850.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EPF6016ATC144-3 Overview

The Intel EPF6016ATC144-3 is a FLEX 6000 family Field Programmable Gate Array (FPGA) integrating 16,000 gates, 1,320 logic cells, and 117 user I/Os in a 144-pin TQFP package with -3 (faster) speed grade. Built on a 0.42 µm CMOS SRAM-look-up-table architecture, the device operates from a 3.3 V core supply (VCCINT) and supports 2.5 V / 3.3 V / 5.0 V I/O via VCCIO banking.

A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells, all customized via SRAM-based configuration memory. FPGAs sit within the broader Programmable Logic hierarchy: PLD -> CPLD -> FPGA -> SoC FPGA, and serve as the lowest-cost / lowest-power option for glue logic, bus bridging, and low-density state-machine replacement compared with higher-density families.

Key features include 132 Logic Array Blocks (LABs) each containing 10 Logic Elements (LEs), dedicated carry and cascade chains for high-speed arithmetic and wide input functions, embedded IEEE 1149.1 JTAG boundary-scan support, and an in-system programmability (ISP) interface. The TQFP-144 footprint is shared across most FLEX 6000 densities via Altera's SameFrame pin-compatibility program, allowing designers to migrate designs across density points without PCB rework.

Architecturally, the FLEX 6000 uses a continuous, hierarchical interconnect network (FastTrack) that delivers predictable timing across the device. The -3 speed grade targets internal frequencies up to 142.86 MHz, suitable for peripheral bus bridges, custom peripherals, and reconfigurable I/O expansion. The SRAM configuration cell requires a configuration device (e.g., EPC2) or JTAG download at every power-up.

Typical applications include glue-logic integration in telecom line cards, industrial control boards, and legacy peripheral bus (PCI, ISA) bridge implementations, where its low cost and moderate density outperform mask-programmed gate arrays for low- to mid-volume production. The part is also used for prototyping where rapid design iteration is required.

When designing with the EPF6016ATC144-3, ensure VCCINT is tied to 3.3 V and VCCIO is matched to the connected bus voltage; mismatched rails will damage I/O buffers. Also allocate a configuration PROM (EPC2, EPC4) or JTAG header for in-system programming - the device has no on-chip non-volatile memory.

This page synthesizes distributor pricing, SameFrame drop-in alternatives within the FLEX 6000 family, and practical design notes not aggregated on the manufacturer datasheet.

Drop-in alternatives for EPF6016ATC144-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF6016ATC144-3 (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Configuration Method, Speed Grade.

EPF6010ATC144-3

Intel

Process Technology: 0.42 µm CMOS SRAM

Speed Grade: -3