EPM240ZM68C6N - 192 Macrocell CPLD 7.5ns 68-MBGA | Intel / Altera
MPN: EPM240ZM68C6N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.2 | $9.20 |
| 10 | $8.3 | $83.00 |
| 100 | $7.1 | $710.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.1 | $5,100.00 |
EPM240ZM68C6N Overview
A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on digital IC that combines multiple PAL-like logic blocks on a single die, with a programmable interconnect matrix routing signals between them. Architecturally, a CPLD sits between small glue-logic gate arrays (a few dozen gates) and full FPGAs (tens of thousands of LUTs with soft cores and SERDES). The MAX II family — to which the EPM240Z belongs — is Altera's (now Intel) zero-power CPLD line: it replaces the classic EEPROM or antifuse cell with on-chip flash configuration memory, eliminating the external boot PROM that legacy MAX devices needed and giving instant-on behavior similar to an FPGA with bitstream pre-loaded into flash.
Key features of the EPM240ZM68C6N include 192 macrocells (~240 logic elements in legacy Altera nomenclature, hence the '240' prefix), 184.1 MHz internal performance, 80 user I/O pins broken into I/O banks, multi-voltage support (1.5 V, 1.8 V, 2.5 V, 3.3 V I/O standards) via banked VCCIO, in-system programmability through JTAG, and low standby current characteristic of the MAX II Z-series. The Micro FBGA-68 package is a chip-scale BGA suited to high-density PCB designs where board area is constrained.
The architecture combines Look-Up Table (LUT) based logic array blocks (LABs) with a global interconnect that fans out across the die. Each macrocell contains a programmable flip-flop, product-term logic, and a configurable output buffer. Compared to discrete 74-series glue logic, the EPM240Z replaces dozens of packages with a single device while adding reconfigurability for late-stage design changes, BOM consolidation, and obsolescence management.
Typical applications include bus-bridging between processors operating at different voltages, glue-logic replacement for 74HC/74LVC series gates, address decoding in microcontroller systems, LED driving and PWM generation, I/O expansion for FPGAs or microcontrollers with insufficient pins, and board-level power sequencing. Designers also use the device in industrial control, motor drive signal conditioning, and portable instrumentation where low standby current matters.
When designing with the EPM240ZM68C6N, mind that the 68-ball Micro FBGA requires X-ray or careful hot-air rework for prototyping and that JTAG chain sharing must be planned if the board already contains an FPGA or another programmable device. The Intel Quartus II (or Quartus Prime Lite) toolchain supports this part with full synthesis, place-and-route, and timing analysis.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes — including JTAG chain sharing and decoupling strategy — to give an engineer a complete view beyond what the manufacturer datasheet alone provides.
Drop-in alternatives for EPM240ZM68C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM240ZM68C6N (same form factor and footprint) — differing in Package, Configuration Memory, Family, Process Technology, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM240ZM100C6N
✅ Drop-In✓ In Stock
$7.1 / Unit
View Datasheet →EPM240ZM100C7N
✅ Drop-In✓ In Stock
$6.1 / Unit
View Datasheet →EPM240ZM100I8N
✅ Drop-In✓ In Stock
$8.45 / Unit
View Datasheet →EPM240ZM68C5N
✅ Drop-In📋 Reference alternative (not in catalog)
EPM240GM100C5N
✅ Drop-In✓ In Stock
$4.75 / Unit
View Datasheet →EPM240M100C5N
✅ Drop-In✓ In Stock
$4.25 / Unit
View Datasheet →EPM240ZM68C6N Maximum Ratings & Electrical Characteristics
| Family | MAX II Z (CPLD) |
| Macrocells | 192 |
| Logic Elements (LE) | 240 |
| Maximum Propagation Delay (tPD) | 7.5 ns |
| Internal Performance (fMAX) | 184.1 MHz |
| Process Technology | 0.18 µm |
| User I/O Count | 80 |
| Number of I/O Banks | 4 |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) |
| Package | 68-ball Micro FBGA (MBGA-68) |
| Mounting Type | Surface Mount (BGA) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) |
| Operating Temperature Range | -40°C to +85°C (commercial, 'C' suffix) |
| RoHS Status | Compliant |
| Lead-Free Finish | Yes |
| MSL Level | 3 (per JEDEC J-STD-020) |
EPM240ZM68C6N Pin Configuration
| Pin A1 | I/O — User I/O (bank 1) |
| Pin A2 | I/O — User I/O (bank 1) |
| Pin A3 | I/O — User I/O (bank 1) |
| Pin A4 | I/O — User I/O (bank 1) |
| Pin A5 | I/O — User I/O (bank 1) |
| Pin A6 | I/O — User I/O (bank 1) |
| Pin A7 | I/O — User I/O (bank 1) |
| Pin A8 | I/O — User I/O (bank 1) |
| Pin B1 | I/O — User I/O (bank 1) |
| Pin B2 | I/O — User I/O (bank 1) |
| Pin B3 | I/O — User I/O (bank 1) |
| Pin B4 | I/O — User I/O (bank 1) |
| Pin B5 | I/O — User I/O (bank 1) |
| Pin B6 | I/O — User I/O (bank 1) |
| Pin B7 | I/O — User I/O (bank 1) |
| Pin B8 | I/O — User I/O (bank 1) |
| Pin C1 | GND — Ground |
| Pin C2 | I/O — User I/O (bank 2) |
| Pin C3 | I/O — User I/O (bank 2) |
| Pin C4 | VCCINT — Core supply 1.8 V |
| Pin C5 | VCCIO1 — Bank 1 I/O supply |
| Pin C6 | I/O — User I/O (bank 3) |
| Pin C7 | I/O — User I/O (bank 3) |
| Pin C8 | GND — Ground |
| Pin D1 | I/O — User I/O (bank 2) |
| Pin D2 | I/O — User I/O (bank 2) |
| Pin D3 | I/O — User I/O (bank 2) |
| Pin D4 | VCCIO2 — Bank 2 I/O supply |
| Pin D5 | GND — Ground |
| Pin D6 | VCCIO3 — Bank 3 I/O supply |
| Pin D7 | I/O — User I/O (bank 3) |
| Pin D8 | I/O — User I/O (bank 3) |
| Pin E1 | TDI — JTAG Test Data In |
| Pin E2 | I/O — User I/O (bank 2) |
| Pin E3 | I/O — User I/O (bank 2) |
| Pin E4 | TMS — JTAG Test Mode Select |
| Pin E5 | TCK — JTAG Test Clock |
| Pin E6 | I/O — User I/O (bank 3) |
| Pin E7 | I/O — User I/O (bank 3) |
| Pin E8 | TDO — JTAG Test Data Out |
| Pin F1 | I/O — User I/O (bank 2) |
| Pin F2 | I/O — User I/O (bank 2) |
| Pin F3 | I/O — User I/O (bank 2) |
| Pin F4 | nCONFIG — Configuration control (pull-up to VCCIO) |
| Pin F5 | nSTATUS — Configuration status (open-drain) |
| Pin F6 | I/O — User I/O (bank 3) |
| Pin F7 | I/O — User I/O (bank 3) |
| Pin F8 | I/O — User I/O (bank 3) |
| Pin G1 | GND — Ground |
| Pin G2 | I/O — User I/O (bank 4) |
| Pin G3 | I/O — User I/O (bank 4) |
| Pin G4 | VCCIO4 — Bank 4 I/O supply |
| Pin G5 | GND — Ground |
| Pin G6 | I/O — User I/O (bank 4) |
| Pin G7 | I/O — User I/O (bank 4) |
| Pin G8 | GND — Ground |
| Pin H1 | I/O — User I/O (bank 4) |
| Pin H2 | I/O — User I/O (bank 4) |
| Pin H3 | I/O — User I/O (bank 4) |
| Pin H4 | I/O — User I/O (bank 4) |
| Pin H5 | I/O — User I/O (bank 4) |
| Pin H6 | I/O — User I/O (bank 4) |
| Pin H7 | I/O — User I/O (bank 4) |
| Pin H8 | I/O — User I/O (bank 4) |
| Pin J1 | I/O — User I/O (bank 4) |
| Pin J2 | I/O — User I/O (bank 4) |
| Pin J3 | I/O — User I/O (bank 4) |
| Pin J4 | I/O — User I/O (bank 4) |
| Pin J5 | I/O — User I/O (bank 4) |
| Pin J6 | I/O — User I/O (bank 4) |
| Pin J7 | I/O — User I/O (bank 4) |
| Pin J8 | I/O — User I/O (bank 4) |
Typical Applications
EPM240ZM68C6N is suitable for 7 applications: Microcontroller I/O Expansion and Glue Logic, Voltage-Translation Bus Bridge, Industrial Control and Sensor Aggregation, LED Driving and PWM Control, Legacy 74-Series Logic Consolidation, JTAG Chain Master / FPGA Configuration Manager, Address Decoding and Chip-Select Generation.
Microcontroller I/O Expansion and Glue Logic
The EPM240ZM68C6N is well suited as a low-latency I/O expander for microcontrollers with insufficient pins, replacing dozens of 74LVC/74HC glue-logic packages with a single re-programmable device. Its 7.5 ns pin-to-pin propagation delay and 192 macrocells handle address decoding, chip-select generation, and interrupt aggregation across 80 user I/O. Instant-on flash configuration eliminates boot-PROM complexity typical of SRAM FPGAs, while 4 VCCIO banks let the CPLD interface directly with 1.8 V MCUs and 3.3 V peripherals in the same design.
Recommended
Voltage-Translation Bus Bridge
Mixed-voltage systems — for example, a 1.8 V application processor talking to 3.3 V sensors — typically need bus-bridging logic. The EPM240ZM68C6N's 4 I/O banks each support independent VCCIO levels (1.5/1.8/2.5/3.3 V), enabling direct voltage translation across 80 channels in one device. This eliminates discrete level-shifter ICs, simplifies PCB layout, and provides reconfigurable direction control. Combined with 7.5 ns propagation delay, the bridge meets asynchronous memory and peripheral timing without additional pipeline registers.
Recommended
Industrial Control and Sensor Aggregation
Industrial controllers aggregate inputs from sensors, switches, and field-bus nodes with deterministic latency. The EPM240ZM68C6N's MAX II Z architecture delivers low standby current, instant-on behaviour, and predictable timing under all temperature conditions in its -40°C to +85°C commercial range. 192 macrocells handle PWM generation, encoder decoding, and fault-condition logic with deterministic 7.5 ns delays. With on-chip flash configuration, the design survives factory programming and field updates via JTAG without external boot components.
Recommended
LED Driving and PWM Control
Multi-channel LED drivers, RGB lighting controllers, and animation PWM generators benefit from the EPM240ZM68C6N's deterministic timing and 80 user I/O. Each macrocell generates a phase-shifted PWM channel, and the 7.5 ns propagation delay supports high-frequency PWM for dimming precision. The 4-bank VCCIO allows direct interfacing with 5 V LED strings and 3.3 V logic without level shifters. On-chip flash configuration provides instant LED pattern start-up at power-on, critical for status indicators and signage.
Recommended
Legacy 74-Series Logic Consolidation
When a design uses dozens of discrete 74LVC/74HC glue-logic gates, the EPM240ZM68C6N consolidates these into a single re-programmable device, reducing BOM cost, PCB area, and assembly labour. The 192 macrocells replace approximately 30 to 50 standard SSI packages, while preserving the same logic behaviour. Late-stage design changes, BOM obsolescence, and variant SKUs are absorbed by simply re-programming the flash — no board respins required.
Recommended
JTAG Chain Master / FPGA Configuration Manager
In systems where an FPGA requires boot management or where multiple programmable devices share one JTAG header, the EPM240ZM68C6N acts as a JTAG chain master. Its 80 user I/O drive TCK, TMS, TDI, TDO signals across downstream FPGAs and CPLDs, while on-chip logic implements boundary-scan tests per IEEE 1149.1. The deterministic 7.5 ns timing and 184.1 MHz internal performance support high-speed JTAG TCK rates. Flash-based configuration lets the chain manager boot instantly without external memory.
Recommended
Address Decoding and Chip-Select Generation
Memory-mapped systems need precise address decoding for SRAM, DRAM, Flash, and peripherals. The EPM240ZM68C6N delivers deterministic 7.5 ns propagation delay for chip-select signals, regardless of address-bus width or fan-out. With 192 macrocells, the device decodes up to 16 to 20 chip-select lines in a single package — replacing discrete 74LS138 / 74LS139 decoders. Multi-voltage bank support enables direct interfacing with 1.8 V memory and 3.3 V peripherals without level shifters.
Recommended
Recommended Products Summary
Engineering reference data for EPM240ZM68C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240ZM100C6N | EPM240ZM100C7N | EPM240ZM100I8N | EPM240ZM68C5N | EPM240GM100C5N | EPM240M100C5N |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 68-ball Micro FBGA (MBGA-68) | 100-pin EQFP (family) | 100-pin EQFP (family) | 100-pin EQFP (family) | 68-ball Micro FBGA — same ball-out | 100-pin MBGA / EQFP | 100-pin EQFP |
| Family | MAX II Z (zero-power) | MAX II Z | MAX II Z | MAX II Z | MAX II Z | MAX II G (non-Z) | MAX II (non-Z) |
| Macrocells / Logic Elements | 192 macrocells / 240 LE | 192 / 240 | 192 / 240 | 192 / 240 | 192 / 240 | 192 / 240 | 192 / 240 |
| Speed Grade (tPD) | C6 — 7.5 ns | C6 — 7.5 ns (same) | C7 — ~9 ns (slower) | I8 — ~10 ns industrial (slower) | C5 — ~5 ns (faster upgrade) | C5 — ~5 ns | C5 — ~5 ns |
| User I/O | 80 | 80 (different package) | 80 | 80 | 80 (same ball-out) | 80 | 80 |
| Operating Temperature | -40°C to +85°C (commercial) | -40°C to +85°C (commercial) | -40°C to +85°C (commercial) | -40°C to +100°C (industrial) | -40°C to +85°C (commercial) | -40°C to +85°C (commercial) | -40°C to +85°C (commercial) |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Configuration Memory | On-chip flash | On-chip flash | On-chip flash | On-chip flash | On-chip flash | On-chip flash | On-chip flash |
Key Differentiators
- Zero-power MAX II Z architecture with on-chip flash (vs EPM240M100C5N (standard MAX II, non-Z))
- 68-ball Micro FBGA for compact board designs (vs EPM240M100C5N (100-pin EQFP))
- C6 speed grade is fully compatible with C7 and I8 grade up-replacements (vs EPM240ZM100C7N and EPM240ZM100I8N)
Design Notes
Estimated: the 68-ball Micro FBGA at 0.5 mm pitch demands 4-layer PCB routing with microvias. Allow continuous ground planes beneath the BGA and stitch vias around the perimeter. Per Intel MAX II Handbook recommendations, place at least one 0.1 µF decoupling capacitor per VCCIO bank and a 1 µF bulk capacitor adjacent to VCCINT. Keep TCK trace under 2 inches and avoid routing JTAG signals near switching power or clock edges to preserve signal integrity.
When sharing the JTAG chain with an FPGA or another CPLD, ensure that nCONFIG and nSTATUS are correctly wired and that each device's TDO feeds the next TDI with proper buffering. The EPM240ZM68C6N supports JTAG chain sharing natively; however, chain length affects TCK maximum frequency. According to the MAX II Device Handbook, keep the total chain below 6 devices at 10 MHz TCK to avoid timing violations.
The MAX II Z-series is designed for low quiescent current, but peak in-rush during flash programming can exceed steady-state by 30 to 50 mA. Ensure the 1.8 V VCCINT regulator can source at least 200 mA transient. Use a 4.7 µF tantalum + 0.1 µF ceramic bypass combination at the device power pin. Estimated: in-rush at flash programming approximates 100 to 150 mA peak for ~50 ms.
Do not confuse the 68-MBGA package with the 100-pin EQFP — the ball-out is not interchangeable and a PCB redesign is required. Verify with the Quartus pin planner that each user I/O ball is correctly assigned to its VCCIO bank. Banked voltage violation (driving 3.3 V into a 1.8 V bank) damages the I/O cells permanently. Per Intel guidelines, always enable unused I/O pins as inputs with internal weak pull-up to avoid floating inputs.
Compliance Information
RoHS and lead-free finish per Altera (now Intel) product marking. Halogen-free status not stated in the captured web data — set to 'unknown' rather than assumed. AEC-Q100 not applicable: MAX II Z is not qualified for automotive under-grade customers should choose the EPM240Z automotive variants where AEC-Q100 is required.
