5M80ZM64C4N - MAX V CPLD 64 Logic Elements 64-MBGA | Intel / Altera
MPN: 5M80ZM64C4N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.52 | $2.52 |
| 10 | $2.27 | $22.70 |
| 100 | $2.02 | $202.00 |
| 500 | $1.78 | $890.00 |
| 1,000 | $1.55 | $1,550.00 |
Drop-in alternatives for 5M80ZM64C4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5M80ZE64C4N
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View Datasheet →5M40ZE64C4N
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View Datasheet →5M80ZM64C4N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device | 5M80Z |
| Logic Elements (LE) | 64 |
| Macro Cells | 64 |
| Maximum User I/O | 79 |
| User Flash Memory | 30 Kbit |
| User SRAM | 8 Kbit |
| Maximum Operating Frequency | 184.1 MHz |
| Pin-to-Pin Logic Delay (tPD1) | 7.5 ns |
| Core Supply Voltage | 1.8 V |
| Multi-Volt I/O Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Package | 64-ball MBGA (Micro FBGA), 4.5 mm × 4.5 mm, 0.5 mm pitch |
| Configuration Memory | Non-volatile on-chip flash |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature (Commercial) | 0 °C to +85 °C |
| RoHS Status | Compliant |
5M80ZM64C4N 64-ball mbga (micro fbga), 4.5 mm × 4.5 mm, 0.5 mm pitch Pin Configuration Guide
Complete pinout information for 5M80ZM64C4N (64-ball mbga (micro fbga), 4.5 mm × 4.5 mm, 0.5 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 5M80ZM64C4N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZM64C4N is suitable for 6 applications: I2C / SPI Bus Multiplexing, Address Decoding & ChipSelect Generation, Power Supply Sequencing, I/O Voltage Translation (1.8/2.5/3.3/5 V), Discrete 74-Series Logic Replacement, LED Display & Signage Control.
I2C / SPI Bus Multiplexing
The 5M80ZM64C4N is well suited to multiplexing I2C and SPI buses between a host microcontroller and multiple peripherals, where its 7.5 ns pin-to-pin delay and 64 LUTs are more than enough to implement 4-to-1 channel selectors, address translators, and bus arbiter state machines. With 79 user I/Os in the 64-ball MBGA, the device can drive up to 4 SPI peripherals (8 lines each at most) or fan an I2C bus out to many slaves. Its non-volatile instant-on configuration removes the need for a boot PROM, so the bus-mux is operational before the host MCU finishes its own boot sequence - critical in systems where peripherals must be live during host reset.
Recommended
Address Decoding & ChipSelect Generation
For address decoding and ChipSelect generation in microprocessor systems, the 5M80ZM64C4N's 8-input LUTs allow wide address ranges to be decoded in a single logic level - a useful property for decoding 24-bit address buses where 5M80Z LUTs map directly to the upper address bits. The 64-LE / 64-macro-cell fabric comfortably handles 8-16 active-low ChipSelect outputs with registered enables, and the 184 MHz fMAX keeps the decoded strobe well ahead of typical 50-100 MHz host bus cycles. Because the configuration is flash-backed, the ChipSelect map survives power cycles with no extra logic.
Recommended
Power Supply Sequencing
The 5M80ZM64C4N is frequently used as a multi-rail power sequencer in FPGA, ASIC, and SoC boards where several rails must come up in a defined order to meet in-rush and POR requirements. Its 64 macro cells implement per-rail enable state machines with adjustable delays set by internal counters, and its 1.8 V core plus 1.8/2.5/3.3/5.0 V I/O banks let it interface directly to enable pins on most POL regulators without level shifters. The instant-on behaviour ensures the rails are sequenced correctly even after a brown-out, eliminating the race conditions that discrete RC sequencers suffer.
Recommended
I/O Voltage Translation (1.8/2.5/3.3/5 V)
The 5M80ZM64C4N's multi-volt I/O banks make it a natural voltage translator between legacy 5 V peripherals and modern 1.8 V or 3.3 V microcontrollers. Each user I/O can be configured independently for 1.8, 2.5, 3.3, or 5.0 V output levels, so a single device can bridge a 5 V parallel bus to a 1.8 V camera interface in the same board. With 79 user I/Os available in the MBGA, the part handles full 16-bit data plus 8-bit control buses; the 7.5 ns tPD1 adds only modest latency versus a passive level shifter.
Recommended
Discrete 74-Series Logic Replacement
Designers frequently replace a board of 74HC/74AHC glue-logic chips with a single 5M80ZM64C4N, collapsing inventory and PCB area. The 64 LUTs in the MBGA package can map dozens of small gates, latches, and one-shots into one device, and re-spinning the design means re-programming the flash - no new BOM or layout. The 30 Kbit user flash also stores board-revision codes and serial numbers, useful for traceability that discrete logic cannot provide.
Recommended
LED Display & Signage Control
The 5M80ZM64C4N's 79 user I/Os and deterministic 7.5 ns timing make it a popular scan-matrix controller for small LED dot-matrix and 7-segment displays, as well as for addressable LED strips (WS2812 / SK6812). The LUT-based fabric drives row/column scanning at up to a few MHz refresh rates, while the user flash stores lookup tables for fonts and animation frames. Its non-volatile configuration means LED signs resume their previous state immediately after power-on - useful in retail and signage where blanking on boot is unacceptable.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZM64C4N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M80ZE64C4N | 5M80ZE64C5N | 5M80ZE64I5N | 5M80ZE64A5N | 5M40ZE64C4N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 64-ball MBGA | 64-ball MBGA - same | 64-ball MBGA - same | 64-ball MBGA - same | 64-ball MBGA - same | 64-ball MBGA - same |
| Logic Elements | 64 | 64 | 64 | 64 | 64 | 40 |
| Macro Cells | 64 | 64 | 64 | 64 | 64 | 40 |
| Maximum User I/O | 79 | 79 | 79 | 79 | 79 | [DATA_NEEDED] |
| Pin-to-Pin Delay (tPD1) | 7.5 ns | 7.5 ns | ~9 ns | ~9 ns | ~10 ns | 7.5 ns |
| Maximum Frequency | 184.1 MHz | 184.1 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Operating Temperature | 0 to +85 C (Commercial) | 0 to +85 C | 0 to +85 C | -40 to +100 C (Industrial) | 0 to +85 C | 0 to +85 C |
| User Flash | 30 Kbit | 30 Kbit | 30 Kbit | 30 Kbit | 30 Kbit | 30 Kbit |
Key Differentiators
- Drop-in same-footprint across C4/C5/A5/I5 speed and temperature grades (vs 5M80ZE64C5N / 5M80ZE64I5N / 5M80ZE64A5N)
- Higher LE count for wider decode trees (vs 5M40ZE64C4N)
- Non-volatile instant-on configuration with 30 Kbit user flash (vs 5M80ZE64C4N (same part, listed for clarity))
Design Notes
The 64-ball MBGA uses a 0.5 mm ball pitch on a 4.5 mm × 4.5 mm body. Use a 4-layer PCB with a continuous ground plane beneath the part and micro-via-in-pad (or dog-bone fan-out) for the inner balls. Solder paste stencil apertures of 0.30-0.35 mm with 0.10-0.13 mm thickness give reliable reflow on ENIG or OSP finishes. Hand-soldering is impractical - plan on reflow or hot-air rework with a preheater.
The 5M80ZM64C4N requires a clean 1.8 V core supply. Decouple each VCC pin with a 0.1 µF X7R 0402 ceramic placed within 2 mm of the ball, and add one 10 µF bulk capacitor near the package. The multi-volt I/O banks are powered separately from the VCCIO pins; tie unused VCCIO pins to the same rail as the active bank (do not leave them floating) so internal ESD structures are biased correctly.
Reserve the four JTAG balls (TCK, TMS, TDI, TDO, plus TRST if present) for a dedicated programming header, even if in-system programming is not used in production - field firmware updates are far easier with JTAG access. Keep the JTAG traces short (<50 mm) and isolate them from switching signals. Add a 10 kΩ pull-up on TCK and TDI, and a 10 kΩ pull-up on TMS as recommended in the MAX V handbook.
Do not confuse the 5M80Z 'M' (64-ball MBGA) pin-out with the 'E' (64-ball MBGA, different revision) or 'T' (TQFP) packages - the ball maps differ between packages even though the die is identical. When porting a MAX II design to MAX V, regenerate the I/O assignments from scratch and re-validate the pin map against the MAX V pin-out file - MAX II used slightly different JTAG ball assignments.
Compliance Information
RoHS and lead-free compliance confirmed by Intel / Altera product family datasheet and distributor parametric pages. REACH and conflict-mineral status not explicitly listed in the verified web data - marked as unknown.
