5M80ZM68C4N - MAX V CPLD, 80 LEs, 68-ball MBGA | Intel
MPN: 5M80ZM68C4N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.2 | $4.20 |
| 10 | $3.78 | $37.80 |
| 100 | $3.36 | $336.00 |
| 500 | $2.94 | $1,470.00 |
| 1,000 | $2.52 | $2,520.00 |
Drop-in alternatives for 5M80ZM68C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet β5M80ZM68C4N Maximum Ratings & Electrical Characteristics
| Series | MAX V |
| Device Family | 5M80Z |
| Logic Elements (LE) | 80 |
| Maximum User I/O | 160 (device-dependent) |
| Package | 68-ball MBGA (Micro FineLine BGA) |
| Speed Grade | -4 |
| Operating Temperature | 0C to +85C (Commercial) |
| Core Voltage | 1.8 V |
| I/O Voltage Support | 1.2 V to 3.3 V LVCMOS / LVTTL |
| Configuration Memory | Internal non-volatile flash |
| Program Interface | JTAG (IEEE 1149.1) / ISP |
| Process | 0.30 um CMOS, 6 metal layers |
| Typical Static Power | 2.5 mW |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (BGA) |
5M80ZM68C4N Pin Configuration
| Pin A1 | I/O β User I/O (bank 1) |
| Pin A2 | I/O β User I/O (bank 1) |
| Pin A3 | I/O β User I/O (bank 1) |
| Pin A4 | I/O β User I/O (bank 1) |
| Pin A5 | I/O β User I/O (bank 1) |
| Pin B1 | I/O β User I/O (bank 1) |
| Pin B2 | I/O β User I/O (bank 1) |
| Pin B3 | GND β Ground |
| Pin B4 | I/O β User I/O (bank 1) |
| Pin B5 | I/O β User I/O (bank 1) |
| Pin C1 | I/O β User I/O (bank 2) |
| Pin C2 | I/O β User I/O (bank 2) |
| Pin C3 | I/O β User I/O (bank 2) |
| Pin C4 | I/O β User I/O (bank 2) |
| Pin C5 | I/O β User I/O (bank 2) |
| Pin D1 | I/O β User I/O (bank 2) |
| Pin D2 | I/O β User I/O (bank 2) |
| Pin D3 | VCCIO1 β I/O bank 1 supply (1.2 V to 3.3 V) |
| Pin D4 | VCCIO2 β I/O bank 2 supply (1.2 V to 3.3 V) |
| Pin D5 | I/O β User I/O (bank 2) |
| Pin E1 | I/O β User I/O (bank 3) |
| Pin E2 | I/O β User I/O (bank 3) |
| Pin E3 | VCCINT β Core supply (1.8 V) |
| Pin E4 | GND β Ground |
| Pin E5 | I/O β User I/O (bank 3) |
| Pin F1 | I/O β User I/O (bank 3) |
| Pin F2 | I/O β User I/O (bank 3) |
| Pin F3 | VCCIO3 β I/O bank 3 supply (1.2 V to 3.3 V) |
| Pin F4 | VCCIO4 β I/O bank 4 supply (1.2 V to 3.3 V) |
| Pin F5 | I/O β User I/O (bank 3) |
| Pin G1 | I/O β User I/O (bank 4) |
| Pin G2 | I/O β User I/O (bank 4) |
| Pin G3 | I/O β User I/O (bank 4) |
| Pin G4 | I/O β User I/O (bank 4) |
| Pin G5 | I/O β User I/O (bank 4) |
| Pin H1 | I/O β User I/O (bank 4) |
| Pin H2 | I/O β User I/O (bank 4) |
| Pin H3 | GND β Ground |
| Pin H4 | I/O β User I/O (bank 4) |
| Pin H5 | I/O β User I/O (bank 4) |
| Pin J1 | I/O β User I/O (bank 5) |
| Pin J2 | I/O β User I/O (bank 5) |
| Pin J3 | I/O β User I/O (bank 5) |
| Pin J4 | I/O β User I/O (bank 5) |
| Pin J5 | I/O β User I/O (bank 5) |
| Pin K1 | I/O β User I/O (bank 5) |
| Pin K2 | I/O β User I/O (bank 5) |
| Pin K3 | VCCIO5 β I/O bank 5 supply (1.2 V to 3.3 V) |
| Pin K4 | VCCIO6 β I/O bank 6 supply (1.2 V to 3.3 V) |
| Pin K5 | I/O β User I/O (bank 5) |
| Pin L1 | I/O β User I/O (bank 6) |
| Pin L2 | I/O β User I/O (bank 6) |
| Pin L3 | VCCINT β Core supply (1.8 V) |
| Pin L4 | GND β Ground |
| Pin L5 | I/O β User I/O (bank 6) |
| Pin M1 | I/O β User I/O (bank 6) |
| Pin M2 | I/O β User I/O (bank 6) |
| Pin M3 | VCCIO7 β I/O bank 7 supply (1.2 V to 3.3 V) |
| Pin M4 | VCCIO8 β I/O bank 8 supply (1.2 V to 3.3 V) |
| Pin M5 | I/O β User I/O (bank 6) |
| Pin N1 | I/O β User I/O (bank 7) |
| Pin N2 | I/O β User I/O (bank 7) |
| Pin N3 | I/O β User I/O (bank 7) |
| Pin N4 | I/O β User I/O (bank 7) |
| Pin N5 | I/O β User I/O (bank 7) |
| Pin P1 | I/O β User I/O (bank 8) |
| Pin P2 | I/O β User I/O (bank 8) |
| Pin P3 | GND β Ground |
| Pin P4 | I/O β User I/O (bank 8) |
| Pin P5 | I/O β User I/O (bank 8) |
| Pin TDO | TDO β JTAG Test Data Out |
| Pin TMS | TMS β JTAG Test Mode Select |
| Pin TCK | TCK β JTAG Test Clock |
| Pin TDI | TDI β JTAG Test Data In |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZM68C4N is suitable for 7 applications: I/O Expansion and Voltage Translation, Power Sequencing and Reset Distribution, Board-Level Glue Logic Replacement, Bus Decoding and Address Mapping, LED Control and Display Driving, Industrial Control Interfaces, Communications Equipment Glue Logic.
I/O Expansion and Voltage Translation
The 5M80ZM68C4N's 80 logic elements and MultiVolt I/O bank support (1.2 V to 3.3 V LVCMOS/LVTTL) make it a natural fit for expanding a microcontroller or ASIC's GPIO count and bridging mixed-voltage domains. The internal flash configuration provides instant-on behavior at power-up, eliminating the boot-PROM footprint, and the JTAG ISP interface allows field reprogramming for I/O map updates. With tPD under 10 ns in the -4 speed grade and 160 user I/O pins, the device can implement multiple 8-bit or 16-bit bus bridges on a single chip, reducing board area versus discrete 74-series logic translators.
Recommended
Power Sequencing and Reset Distribution
The 5M80ZM68C4N is well-suited to multi-rail power-up sequencing in systems with FPGAs, ASICs, and DSPs. Its instant-on, non-volatile flash configuration boots deterministically at POR, and its 1.8 V core with 3.3 V-tolerant I/O lets it drive enable pins of downstream regulators and reset generators without level shifters. The 80 LEs are sufficient to implement cascaded delay chains, watchdog timers, and fault-OR logic for 4 to 8 rails. Compared to a microcontroller or sequencer IC, the CPLD approach offers lower latency, no firmware update burden, and immunity to code-bricks.
Recommended
Board-Level Glue Logic Replacement
Designers consolidating discrete 74-series glue logic (address decoders, chip-select generators, bus arbiters, parity generators) onto a single programmable device choose the 5M80ZM68C4N for its deterministic timing and zero-NRE programmable architecture. With 80 LEs and a -4 speed grade offering predictable pin-to-pin delays of around 7 ns, the device replaces 5 to 15 discrete SSI/MSI packages. The internal flash-backed configuration also prevents unauthorized bitstream inspection, an advantage over SRAM-based alternatives that boot from external PROMs.
Recommended
Bus Decoding and Address Mapping
Memory-mapped bus decoding in embedded systems, where a processor accesses multiple peripherals over a shared address/data bus, is a canonical use case for the 5M80ZM68C4N. The device's wide-input macrocells can decode 16 to 24 address lines plus chip-select and read/write strobes within a single package. Its non-volatile flash configuration means decode maps load at POR with zero latency, and JTAG ISP enables last-minute map changes without re-spinning the board. The 68-ball MBGA footprint is small enough for placement near the processor without crowding the routing channels.
Recommended
LED Control and Display Driving
The 5M80ZM68C4N drives multi-channel LED arrays, character LCDs, and seven-segment displays in industrial HMIs, where its 80 LEs and up to 160 user I/O pins can scan 8 to 16 digits or 64 to 128 LEDs without external drivers. The 1.8 V core with 3.3 V I/O provides clean CMOS drive levels for common-cathode displays, and the flash-backed configuration means the display pattern is retained through power cycles without boot delay. Designers value the deterministic scan timing for reducing flicker versus MCU-driven PWM approaches.
Recommended
Industrial Control Interfaces
The 5M80ZM68C4N is widely used as a bridge between industrial fieldbus controllers and backplane logic in PLCs, motor drives, and process instrumentation. Its MultiVolt I/O supports 1.2 V to 3.3 V logic levels required by modern SoCs while remaining tolerant of legacy 5 V signals through external resistors. The commercial 0C to +85C temperature grade covers most indoor cabinet installations; for harsher environments the pin-compatible 5M80ZM68I5N extends coverage to -40C to +100C. The JTAG ISP allows firmware updates on the production line without removing the device.
Recommended
Communications Equipment Glue Logic
In routers, switches, and base stations the 5M80ZM68C4N serves as deterministic glue logic between network processors, PHYs, and SERDES devices. Its predictable tPD of around 7 ns at -4 speed grade makes it ideal for skew matching across parallel interfaces, while the instant-on flash configuration guarantees known states during system bring-up. The 68-ball MBGA's 0.5 mm pitch supports dense board layouts typical in communications hardware, and the 1.8 V core draws only a few milliwatts of static power, easing thermal budgets in sealed enclosures.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZM68C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M80ZM68A5N | 5M80ZM68C5N | 5M80ZM68I5N | 5M160ZM68C4N |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 68-ball MBGA | 68-ball MBGA (same) | 68-ball MBGA (same) | 68-ball MBGA (same) | 68-ball MBGA (same) |
| Logic Elements | 80 | 80 | 80 | 80 | 160 |
| Speed Grade | -4 | -5 (faster) | -5 (faster) | -5 (faster) | -4 (same) |
| Temperature Grade | Commercial 0C to +85C | Commercial 0C to +85C | Commercial 0C to +85C | Industrial -40C to +100C | Commercial 0C to +85C |
| Configuration Memory | Internal flash | Internal flash | Internal flash | Internal flash | Internal flash |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes |
| Typical 1k Price (USD, as of 2026-09-06) | 2.52 | 2.75 (estimated) | 2.60 (estimated) | 3.20 (estimated) | 4.50 (estimated) |
Key Differentiators
- Non-volatile flash configuration vs SRAM-based FPGAs (vs Generic SRAM FPGAs in same logic density)
- Same 68-ball MBGA across speed and temperature grades (vs 5M80ZE64C5N (64-ball EQFP package))
- MultiVolt I/O across 1.2 V to 3.3 V without level shifters (vs Discrete 74-series logic translators)
Design Notes
The 5M80ZM68C4N requires a clean 1.8 V core supply (VCCINT) plus one or more 1.2 V to 3.3 V I/O bank supplies (VCCIO1..VCCIO8). Each VCCIO pin must be decoupled with a 0.1 uF X7R ceramic capacitor placed within 3 mm of the package ball, plus a 10 uF bulk capacitor at the regulator output. Estimated: with eight I/O banks switching at moderate edge rates, peak current can reach 200 mA; verify with Quartus II PowerPlay analysis for your design.
The 68-ball MBGA uses 0.5 mm ball pitch on a 5 mm x 5 mm body. Route signals on the top layer with escape vias in a dog-bone pattern, keep via-in-pad to a minimum, and provide a continuous ground plane on layer 2 for return-current paths. Solder paste stencil apertures should be 0.4 mm with 0.1 mm reduction to prevent ball collapse during reflow.
For high-speed I/O (above 100 MHz) on the 5M80ZM68C4N, use 50 ohm microstrip traces with length matching within 5 ps across parallel buses. The MAX V device's I/O slew rate is programmable in Quartus II; for EMI-sensitive applications, select slow slew rate to reduce harmonic content. JTAG signals (TCK, TMS, TDI, TDO) should be kept short and routed away from switching I/O to avoid coupling.
Do not leave unused I/O pins floating; configure them as outputs driving ground or as inputs with internal pull-up enabled to avoid shoot-through current. Verify the Quartus II pin assignment file (.pin) matches the 68-ball MBGA ball map before generating the programming file. The device's flash configuration is non-volatile, but design changes require a full JTAG erase and reprogram cycle of approximately 3 seconds.
Compliance Information
RoHS and lead-free per Intel MAX V family product environmental compliance. Halogen-free status not explicitly stated in the provided data; set to unknown. AEC-Q100 not applicable for commercial-temperature CPLD; industrial-temperature 5M80ZM68I5N is the ruggedized variant.
