EP20K400GI655-3 - APEX 20KE 400K Gates FPGA | Altera (Intel PSG)
MPN: EP20K400GI655-3 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $82.5 | $825.00 |
| 50 | $72 | $3,600.00 |
| 100 | $65 | $6,500.00 |
| 500 | $55 | $27,500.00 |
EP20K400GI655-3 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be re-programmed to implement arbitrary digital circuits. FPGAs sit in the programmable logic hierarchy between ASICs (custom-fabricated, high-NRE) and CPLDs (smaller, non-volatile, deterministic delay). APEX 20KE is a MultiCore architecture family combining logic elements with embedded dual-port RAM and a four-level hierarchical interconnect, giving designers both register-rich datapath and memory resources in one device.
Key features of the EP20K400GI655-3 include 502 maximum user I/Os, 4 dedicated inputs, embedded dual-port RAM with FIFO/LIFO support, a built-in 4-wire IEEE 1149.1 JTAG boundary-scan test interface, and a MultiVolt I/O scheme that lets the I/O banks run at 2.5V or 3.3V independently of the 2.5V core supply. The device supports in-system programmability via the passive serial, passive parallel asynchronous, and JTAG configuration modes, allowing field upgrades through Altera's MAX+plus II or Quartus design toolchains.
Architecturally, the APEX 20KE integrates MegaLAB structures containing 16 Logic Arrays each, with adjacent Embedded System Blocks (ESBs) that provide dual-port RAM and product-term logic. Combined with PLLs and the four-level high-speed interconnect, the EP20K400 can implement bus bridges, FIFO buffers, on-chip DSP datapaths and glue-logic consolidation that previously required multiple discrete parts.
Typical applications include telecommunications line-card glue logic, PCI bus interface bridges, custom peripheral aggregation in industrial controllers, prototype ASIC replacement, and high-speed datapath routing in test & measurement equipment. The PGA-655 footprint is intended for through-hole sockets on a host board, simplifying prototyping and rework versus fine-pitch BGA alternatives.
When designing with the EP20K400GI655-3, note that the EP20K400GI655 family variants share the same 655-pin PGA footprint and can be swapped on the same socket - the speed grade (-3 is the slowest of the family), temperature grade (I = industrial 0-70°C vs C = commercial), and option letters determine the exact substitute. Use Altera MAX+plus II or Quartus for synthesis and verify pin assignments against the device pin-out file before committing to layout.
This page synthesizes distributor pricing, drop-in socket-compatible variants within the APEX 20KE family, and practical design considerations that are not collected in a single location in the manufacturer datasheet.
Drop-in alternatives for EP20K400GI655-3 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400GI655-3 (same form factor and footprint) — differing in Package, Process Technology, Mounting Type, Family, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400GI655-2
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K400GI655-2V
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP20K400GI655-2X
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400GC655-3
✅ Drop-In✓ In Stock
$310 / Unit
View Datasheet →EP20K400GC655-2
✅ Drop-In✓ In Stock
$80 / Unit
View Datasheet →EP20K400GC655-3V
✅ Drop-In✓ In Stock
$160 / Unit
View Datasheet →EP20K400GI655-3 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KE |
| Logic Elements / Cells | 16,640 |
| System Gates | 400,000 (maximum) |
| Maximum User I/O | 502 |
| Dedicated Inputs | 4 |
| Number of Terminals | 655 |
| Package | 655-Pin PGA (Plastic/CPGA, square) |
| JESD-30 Code | S-CPGA-P655 |
| Package Shape | Square |
| Form of Terminal | PIN/PEG (through-hole) |
| Mounting Type | Through-Hole (Socket) |
| Process Technology | CMOS, 2.5V core |
| Core Supply Voltage | 2.5 V |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) |
| Operating Temperature | 0°C to 70°C (Industrial I grade) |
| Speed Grade | -3 (slowest of the EP20K400 family) |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
EP20K400GI655-3 square Pin Configuration Guide
Pin configuration for EP20K400GI655-3 (square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400GI655-3.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400GI655-3 is suitable for 6 applications: Telecommunications Line-Card Glue Logic, PCI / PCI-X Bridge and Expansion Logic, Industrial Controller Peripheral Aggregation, Prototype ASIC Replacement, Test & Measurement Equipment Datapath, Datapath Routing in Imaging and Video Systems.
Telecommunications Line-Card Glue Logic
The EP20K400GI655-3's 400,000 system gates and 502 user I/Os make it well suited to integrate multiple bus bridges, UTOPIA/ATM framing blocks, and protocol converters that previously required several discrete ASICs or CPLDs on a line card. Operating from a 2.5V core with MultiVolt I/O at 2.5V/3.3V, it interfaces directly to legacy 3.3V PHY devices and newer 2.5V framers without level shifters. Designers typically synthesize Utopia-2, POS-PHY Level-2, and custom HDLC blocks into the device while reserving a third of the logic for system-level glue and interrupt aggregation. The PGA-655 socket also simplifies lab bring-up and field replacement in central-office environments.
Recommended
PCI / PCI-X Bridge and Expansion Logic
With 16,640 logic elements and 502 I/Os, the EP20K400GI655-3 can host a 32-bit/33 MHz PCI or 64-bit/66 MHz PCI-X bus bridge alongside custom peripheral aggregation logic. The MultiVolt I/O supports 3.3V PCI signaling directly, and the 2.5V core keeps power dissipation manageable for high-gate-count bridges. Engineers implement target/initiator state machines, configuration-space registers, and arbiter logic in MegaLAB structures, leaving ESB blocks for FIFO buffers used in DMA channels. The PGA-655 footprint provides ample signal-integrity headroom for parallel PCI bus routing compared with fine-pitch BGA variants.
Recommended
Industrial Controller Peripheral Aggregation
The EP20K400GI655-3 integrates motor-control feedback decoding, multi-protocol serial aggregation (RS-485, RS-232, SPI, I2C), and EtherCAT/CANopen bridging on a single FPGA, replacing 3-5 discrete ICs in industrial PLC and motion-controller designs. Its industrial 0-70°C temperature grade and through-hole PGA-655 package suit rugged control-cabinet environments where socket-based replacement simplifies field service. ESB dual-port RAM blocks implement high-speed encoder/decoder FIFOs and rate buffers between deterministic control loops and the host CPU. Designers report total system BOM cost reductions of 30-40% versus discrete logic implementations.
Recommended
Prototype ASIC Replacement
Before committing to a high-NRE ASIC tape-out, design teams frequently use the EP20K400GI655-3 as an in-system prototype for ASIC verification. The 400K-gate capacity accommodates designs up to roughly 200K ASIC gates plus memory, and the JTAG and PPA configuration interfaces allow rapid design-iteration cycles in the lab. The PGA-655 package lets engineers swap a re-programmed part in seconds, accelerating verification schedules. Quartus synthesis and timing analysis on the FPGA then maps closely to the eventual ASIC timing, making the EP20K400 an industry-standard ASIC-prototyping vehicle.
Recommended
Test & Measurement Equipment Datapath
High-end oscilloscopes, logic analyzers, and protocol testers use the EP20K400GI655-3 to route, multiplex, and pre-process high-speed datapath signals. The 502 user I/Os comfortably aggregate multiple 16-bit buses, and the ESB blocks implement deep acquisition FIFOs that buffer samples before forwarding to a DSP or external memory. MultiVolt I/O simplifies interfacing with ECL, LVDS and 3.3V/5V mixed-signal front ends. Through-hole PGA-655 mounting makes the part serviceable in lab-grade test instruments where calibration cycles require periodic FPGA refresh.
Recommended
Datapath Routing in Imaging and Video Systems
Medical imaging, broadcast video routers, and machine-vision systems exploit the EP20K400GI655-3's logic density to implement multi-channel video crosspoint switches, color-space converters, and frame-buffer managers. The 502 I/Os connect to parallel camera-link or DVI/HDMI bridge chips while ESB dual-port RAM provides line/frame buffering between input and output domains. Industrial 0-70°C operation suits imaging workstations in clinical and broadcast environments. Engineers typically synthesize BT.656/BT.1120 timing generators, SDI de-/scramblers, and pixel-domain processing directly into the FPGA.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400GI655-3 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400GI655-2 | EP20K400GC655-3 | EP20K400GC655-2 | EP20K400GC655-3V |
|---|---|---|---|---|---|
| Package | 655-Pin PGA (CPGA) | 655-Pin PGA (CPGA) - same | 655-Pin PGA (CPGA) - same | 655-Pin PGA (CPGA) - same | 655-Pin PGA (CPGA) - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Speed Grade | -3 (slowest) | -2 (faster) | -3 (same) | -2 (faster) | -3 (same) |
| Temperature Grade | Industrial (I), 0-70°C | Industrial (I), 0-70°C | Commercial (C), 0-70°C | Commercial (C), 0-70°C | Commercial (C), 0-70°C |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 |
| Maximum User I/O | 502 | 502 | 502 | 502 | 502 |
| Core Supply Voltage | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Configuration Interface | JTAG / PS / PPA | JTAG / PS / PPA | JTAG / PS / PPA | JTAG / PS / PPA | JTAG / PS / PPA |
Key Differentiators
- Through-hole PGA-655 socket for easy field replacement (vs EP20K400FI672-3 (FineLine BGA-672))
- 502 user I/Os vs 488 in BGA-672 family (vs EP20K400FC672-3 (BGA-672))
- Altera/Intel PSG continuity - no third-party controller risk (vs Cross-brand alternative FPGAs)
Design Notes
Estimated: at typical APEX 20KE utilization of 70% logic and 30 MHz internal toggle rate, the EP20K400GI655-3 core power consumption is roughly 1.5-2.5 W. The CPGA-655 package has a thermal resistance of approximately 8 C/W (junction-to-ambient, still air, no heatsink) and 3 C/W with a moderate clip-on heatsink. Designers should provide at least 50 LFM airflow in enclosed chassis; without airflow, derate utilization above 80% or move to a BGA variant with better theta_JA.
Place bulk 2.5V core decoupling (4x 100 uF tantalum + 10x 0.1 uF ceramic) within 1 cm of each VCCINT pin pair. MultiVolt I/O banks require their own 3.3V or 2.5V decoupling - do not tie VCCIO rails together across banks. Route JTAG chain signals (TCK, TMS, TDI, TDO) with 50 ohm controlled impedance and place a 4.7 kohm pull-up on TCK to prevent unintended configuration during board reset. Altera AN-100 documents the recommended layout for APEX 20KE PGA-655 footprints.
Do not confuse the I (industrial 0-70°C) and C (commercial 0-70°C) suffixes - in APEX 20KE both have the same operating range, but I-grade parts undergo additional screening. Verify that your design tool supports the chosen speed grade: -3 is supported by all Quartus versions up to 13.0sp1 and MAX+plus II 10.23; newer Quartus releases have dropped APEX 20KE support. For new designs, plan a migration path to Cyclone IV/V before the part becomes scarce - the EP20K400GI655-3 has been obsolete since ~2008 and factory stock is exhausted.
The PGA-655 socket introduces approximately 2-3 nH of lead inductance per pin, which is acceptable for signals up to 100 MHz but problematic for LVDS or HSTL clocks above 133 MHz. For high-speed interfaces, AC-terminate clock pairs at the device pin with 100 ohm differential and use Altera's IOE DDR registers. Surface-mount BGA variants (EP20K400FI672, EP20K400FC672) are preferred for new high-speed designs because of superior signal-integrity characteristics.
Compliance Information
Compliance data not found in Verified Web Data - the APEX 20KE family pre-dates widespread RoHS documentation on Altera/Intel PSG product pages. The CPGA-655 package contains lead-bearing solder balls on ceramic substrate typical of pre-2006 Altera products; RoHS exemptions for ceramic PGA packages may apply but were not verified.
